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@@ -287,7 +287,7 @@ static int a5xx_me_init(struct msm_gpu *gpu)
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gpu->funcs->flush(gpu);
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- return gpu->funcs->idle(gpu) ? 0 : -EINVAL;
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+ return a5xx_idle(gpu) ? 0 : -EINVAL;
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}
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static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,
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@@ -638,7 +638,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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OUT_RING(gpu->rb, 0x0F);
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gpu->funcs->flush(gpu);
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- if (!gpu->funcs->idle(gpu))
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+ if (!a5xx_idle(gpu))
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return -EINVAL;
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}
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@@ -655,7 +655,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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OUT_RING(gpu->rb, 0x00000000);
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gpu->funcs->flush(gpu);
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- if (!gpu->funcs->idle(gpu))
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+ if (!a5xx_idle(gpu))
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return -EINVAL;
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} else {
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/* Print a warning so if we die, we know why */
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@@ -732,7 +732,7 @@ static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
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A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT);
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}
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-static bool a5xx_idle(struct msm_gpu *gpu)
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+bool a5xx_idle(struct msm_gpu *gpu)
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{
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/* wait for CP to drain ringbuffer: */
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if (!adreno_idle(gpu))
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@@ -1037,7 +1037,6 @@ static const struct adreno_gpu_funcs funcs = {
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.last_fence = adreno_last_fence,
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.submit = a5xx_submit,
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.flush = adreno_flush,
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- .idle = a5xx_idle,
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.irq = a5xx_irq,
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.destroy = a5xx_destroy,
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#ifdef CONFIG_DEBUG_FS
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