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@@ -94,6 +94,11 @@
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*/
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*/
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#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
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#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
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+/*
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+ * Some controllers have DMA enable/disable register
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+ */
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+#define TMIO_MMC_HAVE_CTL_DMA_REG (1 << 9)
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+
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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