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@@ -429,6 +429,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
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.dev_attr = &dma_dev_attr,
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};
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+/*
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+ * 'tpcc' class
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+ *
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+ */
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+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
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+ .name = "tpcc",
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+};
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+
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+static struct omap_hwmod dra7xx_tpcc_hwmod = {
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+ .name = "tpcc",
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+ .class = &dra7xx_tpcc_hwmod_class,
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+ .clkdm_name = "l3main1_clkdm",
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+ .main_clk = "l3_iclk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'tptc' class
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+ *
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+ */
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+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
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+ .name = "tptc",
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+};
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+
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+/* tptc0 */
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+static struct omap_hwmod dra7xx_tptc0_hwmod = {
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+ .name = "tptc0",
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+ .class = &dra7xx_tptc_hwmod_class,
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+ .clkdm_name = "l3main1_clkdm",
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+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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+ .main_clk = "l3_iclk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_HWCTRL,
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+ },
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+ },
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+};
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+
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+/* tptc1 */
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+static struct omap_hwmod dra7xx_tptc1_hwmod = {
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+ .name = "tptc1",
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+ .class = &dra7xx_tptc_hwmod_class,
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+ .clkdm_name = "l3main1_clkdm",
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+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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+ .main_clk = "l3_iclk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_HWCTRL,
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+ },
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+ },
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+};
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+
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/*
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* 'dss' class
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*
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@@ -1482,8 +1543,7 @@ static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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- SIDLE_SMART_WKUP),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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@@ -1527,34 +1587,72 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
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*
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*/
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+/*
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+ * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
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+ * functionality of OMAP HWMOD layer does not deassert the hardreset lines
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+ * associated with an IP automatically leaving the driver to handle that
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+ * by itself. This does not work for PCIeSS which needs the reset lines
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+ * deasserted for the driver to start accessing registers.
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+ *
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+ * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
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+ * lines after asserting them.
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+ */
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+static int dra7xx_pciess_reset(struct omap_hwmod *oh)
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+{
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+ int i;
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+
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+ for (i = 0; i < oh->rst_lines_cnt; i++) {
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+ omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
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+ omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
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+ }
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+
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+ return 0;
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+}
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+
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static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
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.name = "pcie",
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+ .reset = dra7xx_pciess_reset,
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};
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/* pcie1 */
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+static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
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+ { .name = "pcie", .rst_shift = 0 },
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+};
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+
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static struct omap_hwmod dra7xx_pciess1_hwmod = {
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.name = "pcie1",
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.class = &dra7xx_pciess_hwmod_class,
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.clkdm_name = "pcie_clkdm",
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+ .rst_lines = dra7xx_pciess1_resets,
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+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
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.main_clk = "l4_root_clk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
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+ .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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+/* pcie2 */
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+static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
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+ { .name = "pcie", .rst_shift = 1 },
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+};
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+
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/* pcie2 */
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static struct omap_hwmod dra7xx_pciess2_hwmod = {
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.name = "pcie2",
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.class = &dra7xx_pciess_hwmod_class,
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.clkdm_name = "pcie_clkdm",
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+ .rst_lines = dra7xx_pciess2_resets,
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+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
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.main_clk = "l4_root_clk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
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+ .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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@@ -2549,6 +2647,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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+/* l3_main_1 -> tpcc */
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+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
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+ .master = &dra7xx_l3_main_1_hwmod,
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+ .slave = &dra7xx_tpcc_hwmod,
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+ .clk = "l3_iclk_div",
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* l3_main_1 -> tptc0 */
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+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
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+ .master = &dra7xx_l3_main_1_hwmod,
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+ .slave = &dra7xx_tptc0_hwmod,
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+ .clk = "l3_iclk_div",
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* l3_main_1 -> tptc1 */
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+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
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+ .master = &dra7xx_l3_main_1_hwmod,
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+ .slave = &dra7xx_tptc1_hwmod,
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+ .clk = "l3_iclk_div",
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+ .user = OCP_USER_MPU,
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+};
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+
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static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
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{
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.name = "family",
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@@ -3366,6 +3488,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
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&dra7xx_l3_main_1__mcasp3,
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&dra7xx_gmac__mdio,
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&dra7xx_l4_cfg__dma_system,
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+ &dra7xx_l3_main_1__tpcc,
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+ &dra7xx_l3_main_1__tptc0,
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+ &dra7xx_l3_main_1__tptc1,
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&dra7xx_l3_main_1__dss,
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&dra7xx_l3_main_1__dispc,
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&dra7xx_l3_main_1__hdmi,
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