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@@ -72,7 +72,7 @@
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#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
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#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
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#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
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#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
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-#define PASR (COFNIG_MBAR + 0xc04) /* PCI arbiter status */
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+#define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */
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/*
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/*
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* Definitions for the Global status and control register.
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* Definitions for the Global status and control register.
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Paul Bolle