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@@ -255,8 +255,10 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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if (ret < 0)
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break;
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+
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#ifdef CONFIG_DEBUG_PAGEALLOC
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- if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
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+ if (debug_pagealloc_enabled() &&
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+ (paddr >> PAGE_SHIFT) < linear_map_hash_count)
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linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
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#endif /* CONFIG_DEBUG_PAGEALLOC */
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}
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@@ -512,17 +514,17 @@ static void __init htab_init_page_sizes(void)
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if (mmu_has_feature(MMU_FTR_16M_PAGE))
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memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
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sizeof(mmu_psize_defaults_gp));
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- found:
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-#ifndef CONFIG_DEBUG_PAGEALLOC
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- /*
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- * Pick a size for the linear mapping. Currently, we only support
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- * 16M, 1M and 4K which is the default
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- */
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- if (mmu_psize_defs[MMU_PAGE_16M].shift)
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- mmu_linear_psize = MMU_PAGE_16M;
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- else if (mmu_psize_defs[MMU_PAGE_1M].shift)
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- mmu_linear_psize = MMU_PAGE_1M;
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-#endif /* CONFIG_DEBUG_PAGEALLOC */
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+found:
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+ if (!debug_pagealloc_enabled()) {
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+ /*
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+ * Pick a size for the linear mapping. Currently, we only
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+ * support 16M, 1M and 4K which is the default
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+ */
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+ if (mmu_psize_defs[MMU_PAGE_16M].shift)
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+ mmu_linear_psize = MMU_PAGE_16M;
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+ else if (mmu_psize_defs[MMU_PAGE_1M].shift)
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+ mmu_linear_psize = MMU_PAGE_1M;
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+ }
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#ifdef CONFIG_PPC_64K_PAGES
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/*
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@@ -721,10 +723,12 @@ static void __init htab_initialize(void)
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prot = pgprot_val(PAGE_KERNEL);
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#ifdef CONFIG_DEBUG_PAGEALLOC
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- linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
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- linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
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- 1, ppc64_rma_size));
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- memset(linear_map_hash_slots, 0, linear_map_hash_count);
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+ if (debug_pagealloc_enabled()) {
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+ linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
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+ linear_map_hash_slots = __va(memblock_alloc_base(
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+ linear_map_hash_count, 1, ppc64_rma_size));
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+ memset(linear_map_hash_slots, 0, linear_map_hash_count);
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+ }
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#endif /* CONFIG_DEBUG_PAGEALLOC */
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/* On U3 based machines, we need to reserve the DART area and
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