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@@ -30,6 +30,7 @@
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#define SW_OVERRIDE_MASK BIT(2)
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#define HW_CONTROL_MASK BIT(1)
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#define SW_COLLAPSE_MASK BIT(0)
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+#define GMEM_CLAMP_IO_MASK BIT(0)
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/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
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#define EN_REST_WAIT_VAL (0x2 << 20)
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@@ -140,6 +141,18 @@ static inline void gdsc_clear_mem_on(struct gdsc *sc)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
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}
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+static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
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+{
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+ regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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+ GMEM_CLAMP_IO_MASK, 0);
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+}
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+
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+static inline void gdsc_assert_clamp_io(struct gdsc *sc)
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+{
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+ regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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+ GMEM_CLAMP_IO_MASK, 1);
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+}
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+
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static int gdsc_enable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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@@ -148,6 +161,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_deassert_reset(sc);
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+ if (sc->flags & CLAMP_IO)
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+ gdsc_deassert_clamp_io(sc);
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+
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ret = gdsc_toggle_logic(sc, true);
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if (ret)
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return ret;
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@@ -170,6 +186,7 @@ static int gdsc_enable(struct generic_pm_domain *domain)
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static int gdsc_disable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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+ int ret;
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_assert_reset(sc);
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@@ -177,7 +194,14 @@ static int gdsc_disable(struct generic_pm_domain *domain)
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_clear_mem_on(sc);
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- return gdsc_toggle_logic(sc, false);
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+ ret = gdsc_toggle_logic(sc, false);
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+ if (ret)
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+ return ret;
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+
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+ if (sc->flags & CLAMP_IO)
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+ gdsc_assert_clamp_io(sc);
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+
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+ return 0;
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}
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static int gdsc_init(struct gdsc *sc)
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