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@@ -132,6 +132,8 @@ static void si_dma_stop(struct amdgpu_device *adev)
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rb_cntl &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
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+ if (adev->mman.buffer_funcs_ring == ring)
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+ amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
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ring->ready = false;
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}
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}
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@@ -192,6 +194,9 @@ static int si_dma_start(struct amdgpu_device *adev)
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ring->ready = false;
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return r;
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}
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+
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+ if (adev->mman.buffer_funcs_ring == ring)
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+ amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
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}
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return 0;
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