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@@ -191,6 +191,42 @@
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#include "ns2-clock.dtsi"
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+ pdc0: iproc-pdc0@612c0000 {
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+ compatible = "brcm,iproc-pdc-mbox";
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+ reg = <0x612c0000 0x445>; /* PDC FS0 regs */
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+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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+ #mbox-cells = <1>;
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+ brcm,rx-status-len = <32>;
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+ brcm,use-bcm-hdr;
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+ };
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+
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+ pdc1: iproc-pdc1@612e0000 {
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+ compatible = "brcm,iproc-pdc-mbox";
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+ reg = <0x612e0000 0x445>; /* PDC FS1 regs */
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+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
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+ #mbox-cells = <1>;
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+ brcm,rx-status-len = <32>;
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+ brcm,use-bcm-hdr;
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+ };
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+
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+ pdc2: iproc-pdc2@61300000 {
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+ compatible = "brcm,iproc-pdc-mbox";
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+ reg = <0x61300000 0x445>; /* PDC FS2 regs */
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+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
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+ #mbox-cells = <1>;
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+ brcm,rx-status-len = <32>;
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+ brcm,use-bcm-hdr;
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+ };
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+
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+ pdc3: iproc-pdc3@61320000 {
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+ compatible = "brcm,iproc-pdc-mbox";
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+ reg = <0x61320000 0x445>; /* PDC FS3 regs */
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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+ #mbox-cells = <1>;
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+ brcm,rx-status-len = <32>;
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+ brcm,use-bcm-hdr;
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+ };
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+
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dma0: dma@61360000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x61360000 0x1000>;
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