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@@ -499,31 +499,6 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
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amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
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amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
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}
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}
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-unsigned init_cond_exec(struct amdgpu_ring *ring)
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-{
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- unsigned ret;
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- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
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- amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
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- amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
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- amdgpu_ring_write(ring, 1);
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- ret = ring->wptr;/* this is the offset we need patch later */
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- amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
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- return ret;
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-}
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-
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-void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
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-{
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- unsigned cur;
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- BUG_ON(ring->ring[offset] != 0x55aa55aa);
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-
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- cur = ring->wptr - 1;
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- if (likely(cur > offset))
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- ring->ring[offset] = cur - offset;
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- else
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- ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
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-}
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-
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-
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/**
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/**
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* sdma_v3_0_gfx_stop - stop the gfx async dma engines
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* sdma_v3_0_gfx_stop - stop the gfx async dma engines
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*
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*
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