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@@ -3773,7 +3773,7 @@ static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
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return -EINVAL;
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}
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}
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-
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+#if 0
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if (!pi->pcie_dpm_key_disabled) {
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if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
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result = ci_send_msg_to_smc_with_parameter(rdev,
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@@ -3783,7 +3783,7 @@ static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
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return -EINVAL;
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}
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}
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-
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+#endif
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return 0;
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}
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@@ -4247,6 +4247,14 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev,
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}
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}
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} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
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+ if (!pi->pcie_dpm_key_disabled) {
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+ PPSMC_Result smc_result;
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+
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+ smc_result = ci_send_msg_to_smc(rdev,
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+ PPSMC_MSG_PCIeDPM_UnForceLevel);
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+ if (smc_result != PPSMC_Result_OK)
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+ return -EINVAL;
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+ }
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ret = ci_upload_dpm_level_enable_mask(rdev);
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if (ret)
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return ret;
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