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@@ -37,6 +37,121 @@ qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
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return ptr + (ha->response_q_length * sizeof(response_t));
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}
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+static int
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+qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
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+ uint32_t cram_size, uint32_t *ext_mem, void **nxt)
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+{
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+ int rval;
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+ uint32_t cnt, stat, timer, risc_address, ext_mem_cnt;
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+ uint16_t mb[4];
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+ struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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+
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+ rval = QLA_SUCCESS;
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+ risc_address = ext_mem_cnt = 0;
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+ memset(mb, 0, sizeof(mb));
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+
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+ /* Code RAM. */
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+ risc_address = 0x20000;
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+ WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
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+ clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
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+
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+ for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS;
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+ cnt++, risc_address++) {
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+ WRT_REG_WORD(®->mailbox1, LSW(risc_address));
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+ WRT_REG_WORD(®->mailbox8, MSW(risc_address));
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+ RD_REG_WORD(®->mailbox8);
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+ WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
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+
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+ for (timer = 6000000; timer; timer--) {
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+ /* Check for pending interrupts. */
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+ stat = RD_REG_DWORD(®->host_status);
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+ if (stat & HSRX_RISC_INT) {
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+ stat &= 0xff;
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+
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+ if (stat == 0x1 || stat == 0x2 ||
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+ stat == 0x10 || stat == 0x11) {
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+ set_bit(MBX_INTERRUPT,
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+ &ha->mbx_cmd_flags);
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+
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+ mb[0] = RD_REG_WORD(®->mailbox0);
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+ mb[2] = RD_REG_WORD(®->mailbox2);
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+ mb[3] = RD_REG_WORD(®->mailbox3);
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+
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+ WRT_REG_DWORD(®->hccr,
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+ HCCRX_CLR_RISC_INT);
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+ RD_REG_DWORD(®->hccr);
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+ break;
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+ }
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+
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+ /* Clear this intr; it wasn't a mailbox intr */
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+ WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
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+ RD_REG_DWORD(®->hccr);
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+ }
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+ udelay(5);
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+ }
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+
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+ if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
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+ rval = mb[0] & MBS_MASK;
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+ code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
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+ } else {
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+ rval = QLA_FUNCTION_FAILED;
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+ }
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+ }
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+
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+ if (rval == QLA_SUCCESS) {
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+ /* External Memory. */
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+ risc_address = 0x100000;
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+ ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
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+ WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
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+ clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
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+ }
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+ for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
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+ cnt++, risc_address++) {
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+ WRT_REG_WORD(®->mailbox1, LSW(risc_address));
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+ WRT_REG_WORD(®->mailbox8, MSW(risc_address));
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+ RD_REG_WORD(®->mailbox8);
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+ WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
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+
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+ for (timer = 6000000; timer; timer--) {
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+ /* Check for pending interrupts. */
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+ stat = RD_REG_DWORD(®->host_status);
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+ if (stat & HSRX_RISC_INT) {
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+ stat &= 0xff;
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+
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+ if (stat == 0x1 || stat == 0x2 ||
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+ stat == 0x10 || stat == 0x11) {
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+ set_bit(MBX_INTERRUPT,
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+ &ha->mbx_cmd_flags);
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+
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+ mb[0] = RD_REG_WORD(®->mailbox0);
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+ mb[2] = RD_REG_WORD(®->mailbox2);
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+ mb[3] = RD_REG_WORD(®->mailbox3);
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+
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+ WRT_REG_DWORD(®->hccr,
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+ HCCRX_CLR_RISC_INT);
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+ RD_REG_DWORD(®->hccr);
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+ break;
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+ }
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+
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+ /* Clear this intr; it wasn't a mailbox intr */
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+ WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
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+ RD_REG_DWORD(®->hccr);
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+ }
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+ udelay(5);
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+ }
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+
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+ if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
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+ rval = mb[0] & MBS_MASK;
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+ ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
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+ } else {
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+ rval = QLA_FUNCTION_FAILED;
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+ }
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+ }
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+
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+ *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL;
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+ return rval;
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+}
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+
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/**
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* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
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* @ha: HA context
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@@ -633,11 +748,10 @@ void
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qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
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{
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int rval;
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- uint32_t cnt, timer;
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+ uint32_t cnt;
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uint32_t risc_address;
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- uint16_t mb[4], wd;
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+ uint16_t mb0, wd;
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- uint32_t stat;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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uint32_t __iomem *dmp_reg;
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uint32_t *iter_reg;
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@@ -645,10 +759,9 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
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unsigned long flags;
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struct qla24xx_fw_dump *fw;
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uint32_t ext_mem_cnt;
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- void *eft;
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+ void *nxt;
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risc_address = ext_mem_cnt = 0;
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- memset(mb, 0, sizeof(mb));
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flags = 0;
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if (!hardware_locked)
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@@ -701,250 +814,236 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
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/* Shadow registers. */
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WRT_REG_DWORD(®->iobase_addr, 0x0F70);
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RD_REG_DWORD(®->iobase_addr);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0000000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg));
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0100000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg));
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0200000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg));
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0300000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg));
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0400000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg));
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0500000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg));
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0600000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg));
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+ WRT_REG_DWORD(®->iobase_select, 0xB0000000);
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+ fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
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+
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+ WRT_REG_DWORD(®->iobase_select, 0xB0100000);
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+ fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
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+
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+ WRT_REG_DWORD(®->iobase_select, 0xB0200000);
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+ fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
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+
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+ WRT_REG_DWORD(®->iobase_select, 0xB0300000);
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+ fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
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+
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+ WRT_REG_DWORD(®->iobase_select, 0xB0400000);
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+ fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
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+
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+ WRT_REG_DWORD(®->iobase_select, 0xB0500000);
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+ fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
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+
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+ WRT_REG_DWORD(®->iobase_select, 0xB0600000);
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+ fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
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/* Mailbox registers. */
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- mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
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+ mbx_reg = ®->mailbox0;
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
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/* Transfer sequence registers. */
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iter_reg = fw->xseq_gp_reg;
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WRT_REG_DWORD(®->iobase_addr, 0xBF00);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF10);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF20);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF30);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF40);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF50);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF60);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBF70);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBFE0);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
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fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xBFF0);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
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fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
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/* Receive sequence registers. */
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iter_reg = fw->rseq_gp_reg;
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WRT_REG_DWORD(®->iobase_addr, 0xFF00);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xFF10);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xFF20);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xFF30);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xFF40);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xFF50);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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WRT_REG_DWORD(®->iobase_addr, 0xFF60);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
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+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0xFF70);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0xFFD0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
|
|
|
fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0xFFE0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
|
|
|
fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0xFFF0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
|
|
|
fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* Command DMA registers. */
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7100);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
|
|
|
fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* Queues. */
|
|
|
iter_reg = fw->req0_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7200);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 8; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
|
|
|
+ dmp_reg = ®->iobase_q;
|
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->resp0_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7300);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 8; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
|
|
|
+ dmp_reg = ®->iobase_q;
|
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->req1_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7400);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 8; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
|
|
|
+ dmp_reg = ®->iobase_q;
|
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* Transmit DMA registers. */
|
|
|
iter_reg = fw->xmt0_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7600);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7610);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->xmt1_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7620);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7630);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->xmt2_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7640);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7650);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->xmt3_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7660);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7670);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->xmt4_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7680);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7690);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x76A0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
|
|
|
fw->xmt_data_dma_reg[cnt] =
|
|
|
htonl(RD_REG_DWORD(dmp_reg++));
|
|
@@ -952,221 +1051,221 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
|
|
|
/* Receive DMA registers. */
|
|
|
iter_reg = fw->rcvt0_data_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7700);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7710);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
iter_reg = fw->rcvt1_data_dma_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7720);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7730);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* RISC registers. */
|
|
|
iter_reg = fw->risc_gp_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F00);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F10);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F20);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F30);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F40);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F50);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F60);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F70);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* Local memory controller registers. */
|
|
|
iter_reg = fw->lmc_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3000);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3010);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3020);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3030);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3040);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3050);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x3060);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* Fibre Protocol Module registers. */
|
|
|
iter_reg = fw->fpm_hdw_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4000);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4010);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4020);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4030);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4040);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4050);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4060);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4070);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4080);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x4090);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x40A0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x40B0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
/* Frame Buffer registers. */
|
|
|
iter_reg = fw->fb_hdw_reg;
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6000);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6010);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6020);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6030);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6040);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6100);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6130);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6150);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6170);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x6190);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
WRT_REG_DWORD(®->iobase_addr, 0x61B0);
|
|
|
- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
for (cnt = 0; cnt < 16; cnt++)
|
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
@@ -1187,10 +1286,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
|
|
|
|
|
|
udelay(100);
|
|
|
/* Wait for firmware to complete NVRAM accesses. */
|
|
|
- mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0);
|
|
|
- for (cnt = 10000 ; cnt && mb[0]; cnt--) {
|
|
|
+ mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
|
|
|
+ for (cnt = 10000 ; cnt && mb0; cnt--) {
|
|
|
udelay(5);
|
|
|
- mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0);
|
|
|
+ mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
|
|
|
barrier();
|
|
|
}
|
|
|
|
|
@@ -1214,116 +1313,723 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
|
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
|
}
|
|
|
|
|
|
- /* Memory. */
|
|
|
+ if (rval == QLA_SUCCESS)
|
|
|
+ rval = qla2xxx_dump_memory(ha, fw->code_ram,
|
|
|
+ sizeof(fw->code_ram), fw->ext_mem, &nxt);
|
|
|
+
|
|
|
if (rval == QLA_SUCCESS) {
|
|
|
- /* Code RAM. */
|
|
|
- risc_address = 0x20000;
|
|
|
- WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
|
|
|
- clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
|
|
|
+ nxt = qla2xxx_copy_queues(ha, nxt);
|
|
|
+ if (ha->eft)
|
|
|
+ memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
|
|
|
}
|
|
|
- for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
|
|
|
- cnt++, risc_address++) {
|
|
|
- WRT_REG_WORD(®->mailbox1, LSW(risc_address));
|
|
|
- WRT_REG_WORD(®->mailbox8, MSW(risc_address));
|
|
|
- RD_REG_WORD(®->mailbox8);
|
|
|
- WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
|
|
|
-
|
|
|
- for (timer = 6000000; timer; timer--) {
|
|
|
- /* Check for pending interrupts. */
|
|
|
- stat = RD_REG_DWORD(®->host_status);
|
|
|
- if (stat & HSRX_RISC_INT) {
|
|
|
- stat &= 0xff;
|
|
|
-
|
|
|
- if (stat == 0x1 || stat == 0x2 ||
|
|
|
- stat == 0x10 || stat == 0x11) {
|
|
|
- set_bit(MBX_INTERRUPT,
|
|
|
- &ha->mbx_cmd_flags);
|
|
|
|
|
|
- mb[0] = RD_REG_WORD(®->mailbox0);
|
|
|
- mb[2] = RD_REG_WORD(®->mailbox2);
|
|
|
- mb[3] = RD_REG_WORD(®->mailbox3);
|
|
|
+ if (rval != QLA_SUCCESS) {
|
|
|
+ qla_printk(KERN_WARNING, ha,
|
|
|
+ "Failed to dump firmware (%x)!!!\n", rval);
|
|
|
+ ha->fw_dumped = 0;
|
|
|
|
|
|
- WRT_REG_DWORD(®->hccr,
|
|
|
- HCCRX_CLR_RISC_INT);
|
|
|
- RD_REG_DWORD(®->hccr);
|
|
|
- break;
|
|
|
- }
|
|
|
+ } else {
|
|
|
+ qla_printk(KERN_INFO, ha,
|
|
|
+ "Firmware dump saved to temp buffer (%ld/%p).\n",
|
|
|
+ ha->host_no, ha->fw_dump);
|
|
|
+ ha->fw_dumped = 1;
|
|
|
+ }
|
|
|
|
|
|
- /* Clear this intr; it wasn't a mailbox intr */
|
|
|
- WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
|
|
|
- RD_REG_DWORD(®->hccr);
|
|
|
- }
|
|
|
- udelay(5);
|
|
|
- }
|
|
|
+qla24xx_fw_dump_failed:
|
|
|
+ if (!hardware_locked)
|
|
|
+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
|
+}
|
|
|
|
|
|
- if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
|
|
|
- rval = mb[0] & MBS_MASK;
|
|
|
- fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
|
|
|
- } else {
|
|
|
- rval = QLA_FUNCTION_FAILED;
|
|
|
- }
|
|
|
- }
|
|
|
+void
|
|
|
+qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
|
|
|
+{
|
|
|
+ int rval;
|
|
|
+ uint32_t cnt;
|
|
|
+ uint32_t risc_address;
|
|
|
+ uint16_t mb0, wd;
|
|
|
|
|
|
- if (rval == QLA_SUCCESS) {
|
|
|
- /* External Memory. */
|
|
|
- risc_address = 0x100000;
|
|
|
- ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
|
|
|
- WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
|
|
|
- clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
|
|
|
- }
|
|
|
- for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
|
|
|
- cnt++, risc_address++) {
|
|
|
- WRT_REG_WORD(®->mailbox1, LSW(risc_address));
|
|
|
- WRT_REG_WORD(®->mailbox8, MSW(risc_address));
|
|
|
- RD_REG_WORD(®->mailbox8);
|
|
|
- WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
|
|
|
+ struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
+ uint32_t __iomem *dmp_reg;
|
|
|
+ uint32_t *iter_reg;
|
|
|
+ uint16_t __iomem *mbx_reg;
|
|
|
+ unsigned long flags;
|
|
|
+ struct qla25xx_fw_dump *fw;
|
|
|
+ uint32_t ext_mem_cnt;
|
|
|
+ void *nxt;
|
|
|
|
|
|
- for (timer = 6000000; timer; timer--) {
|
|
|
- /* Check for pending interrupts. */
|
|
|
- stat = RD_REG_DWORD(®->host_status);
|
|
|
- if (stat & HSRX_RISC_INT) {
|
|
|
- stat &= 0xff;
|
|
|
+ risc_address = ext_mem_cnt = 0;
|
|
|
+ flags = 0;
|
|
|
|
|
|
- if (stat == 0x1 || stat == 0x2 ||
|
|
|
- stat == 0x10 || stat == 0x11) {
|
|
|
- set_bit(MBX_INTERRUPT,
|
|
|
- &ha->mbx_cmd_flags);
|
|
|
+ if (!hardware_locked)
|
|
|
+ spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
|
|
|
|
- mb[0] = RD_REG_WORD(®->mailbox0);
|
|
|
- mb[2] = RD_REG_WORD(®->mailbox2);
|
|
|
- mb[3] = RD_REG_WORD(®->mailbox3);
|
|
|
+ if (!ha->fw_dump) {
|
|
|
+ qla_printk(KERN_WARNING, ha,
|
|
|
+ "No buffer available for dump!!!\n");
|
|
|
+ goto qla25xx_fw_dump_failed;
|
|
|
+ }
|
|
|
|
|
|
- WRT_REG_DWORD(®->hccr,
|
|
|
- HCCRX_CLR_RISC_INT);
|
|
|
- RD_REG_DWORD(®->hccr);
|
|
|
- break;
|
|
|
- }
|
|
|
+ if (ha->fw_dumped) {
|
|
|
+ qla_printk(KERN_WARNING, ha,
|
|
|
+ "Firmware has been previously dumped (%p) -- ignoring "
|
|
|
+ "request...\n", ha->fw_dump);
|
|
|
+ goto qla25xx_fw_dump_failed;
|
|
|
+ }
|
|
|
+ fw = &ha->fw_dump->isp.isp25;
|
|
|
+ qla2xxx_prep_dump(ha, ha->fw_dump);
|
|
|
|
|
|
- /* Clear this intr; it wasn't a mailbox intr */
|
|
|
- WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
|
|
|
- RD_REG_DWORD(®->hccr);
|
|
|
- }
|
|
|
- udelay(5);
|
|
|
- }
|
|
|
+ rval = QLA_SUCCESS;
|
|
|
+ fw->host_status = htonl(RD_REG_DWORD(®->host_status));
|
|
|
|
|
|
- if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
|
|
|
- rval = mb[0] & MBS_MASK;
|
|
|
- fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
|
|
|
- } else {
|
|
|
- rval = QLA_FUNCTION_FAILED;
|
|
|
+ /* Pause RISC. */
|
|
|
+ if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) {
|
|
|
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET |
|
|
|
+ HCCRX_CLR_HOST_INT);
|
|
|
+ RD_REG_DWORD(®->hccr); /* PCI Posting. */
|
|
|
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
|
|
|
+ for (cnt = 30000;
|
|
|
+ (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
|
|
|
+ rval == QLA_SUCCESS; cnt--) {
|
|
|
+ if (cnt)
|
|
|
+ udelay(100);
|
|
|
+ else
|
|
|
+ rval = QLA_FUNCTION_TIMEOUT;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (rval == QLA_SUCCESS) {
|
|
|
- eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]);
|
|
|
- if (ha->eft)
|
|
|
- memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size));
|
|
|
- }
|
|
|
+ /* Host interface registers. */
|
|
|
+ dmp_reg = (uint32_t __iomem *)(reg + 0);
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
|
|
|
+ fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
|
|
- if (rval != QLA_SUCCESS) {
|
|
|
- qla_printk(KERN_WARNING, ha,
|
|
|
- "Failed to dump firmware (%x)!!!\n", rval);
|
|
|
- ha->fw_dumped = 0;
|
|
|
+ /* Disable interrupts. */
|
|
|
+ WRT_REG_DWORD(®->ictrl, 0);
|
|
|
+ RD_REG_DWORD(®->ictrl);
|
|
|
+
|
|
|
+ /* Shadow registers. */
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F70);
|
|
|
+ RD_REG_DWORD(®->iobase_addr);
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0000000);
|
|
|
+ fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0100000);
|
|
|
+ fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0200000);
|
|
|
+ fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0300000);
|
|
|
+ fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0400000);
|
|
|
+ fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0500000);
|
|
|
+ fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0600000);
|
|
|
+ fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0700000);
|
|
|
+ fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0800000);
|
|
|
+ fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0900000);
|
|
|
+ fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
|
|
|
+ fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
+
|
|
|
+ /* RISC I/O register. */
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0010);
|
|
|
+ RD_REG_DWORD(®->iobase_addr);
|
|
|
+ fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
|
|
|
+
|
|
|
+ /* Mailbox registers. */
|
|
|
+ mbx_reg = ®->mailbox0;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
|
|
|
+ fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
|
|
|
+
|
|
|
+ /* Transfer sequence registers. */
|
|
|
+ iter_reg = fw->xseq_gp_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF00);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF10);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF20);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF30);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF40);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF50);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF60);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBF70);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->xseq_0_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBFC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBFD0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBFE0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xBFF0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
|
|
|
+ fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Receive sequence registers. */
|
|
|
+ iter_reg = fw->rseq_gp_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF00);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF10);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF20);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF30);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF40);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF50);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF60);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFF70);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->rseq_0_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFFC0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFFD0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFFE0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
|
|
|
+ fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xFFF0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
|
|
|
+ fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Auxiliary sequence registers. */
|
|
|
+ iter_reg = fw->aseq_gp_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB000);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB010);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB020);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB030);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB040);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB050);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB060);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB070);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->aseq_0_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB0C0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB0D0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB0E0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++)
|
|
|
+ fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0xB0F0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++)
|
|
|
+ fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Command DMA registers. */
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7100);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
|
|
|
+ fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Queues. */
|
|
|
+ iter_reg = fw->req0_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7200);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 8; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ dmp_reg = ®->iobase_q;
|
|
|
+ for (cnt = 0; cnt < 7; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->resp0_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7300);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 8; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ dmp_reg = ®->iobase_q;
|
|
|
+ for (cnt = 0; cnt < 7; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->req1_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7400);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 8; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ dmp_reg = ®->iobase_q;
|
|
|
+ for (cnt = 0; cnt < 7; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Transmit DMA registers. */
|
|
|
+ iter_reg = fw->xmt0_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7600);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7610);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->xmt1_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7620);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7630);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->xmt2_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7640);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7650);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->xmt3_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7660);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7670);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->xmt4_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7680);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7690);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x76A0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
|
|
|
+ fw->xmt_data_dma_reg[cnt] =
|
|
|
+ htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Receive DMA registers. */
|
|
|
+ iter_reg = fw->rcvt0_data_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7700);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7710);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ iter_reg = fw->rcvt1_data_dma_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7720);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x7730);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* RISC registers. */
|
|
|
+ iter_reg = fw->risc_gp_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F00);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F10);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F20);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F30);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F40);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F50);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F60);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x0F70);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Local memory controller registers. */
|
|
|
+ iter_reg = fw->lmc_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3000);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3010);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3020);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3030);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3040);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3050);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3060);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x3070);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Fibre Protocol Module registers. */
|
|
|
+ iter_reg = fw->fpm_hdw_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4000);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4010);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4020);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4030);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4040);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4050);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4060);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4070);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4080);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x4090);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x40A0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x40B0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Frame Buffer registers. */
|
|
|
+ iter_reg = fw->fb_hdw_reg;
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6000);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6010);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6020);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6030);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6040);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6100);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6130);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6150);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6170);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6190);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x61B0);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->iobase_addr, 0x6F00);
|
|
|
+ dmp_reg = ®->iobase_window;
|
|
|
+ for (cnt = 0; cnt < 16; cnt++)
|
|
|
+ *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
+
|
|
|
+ /* Reset RISC. */
|
|
|
+ WRT_REG_DWORD(®->ctrl_status,
|
|
|
+ CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
|
|
|
+ for (cnt = 0; cnt < 30000; cnt++) {
|
|
|
+ if ((RD_REG_DWORD(®->ctrl_status) &
|
|
|
+ CSRX_DMA_ACTIVE) == 0)
|
|
|
+ break;
|
|
|
+
|
|
|
+ udelay(10);
|
|
|
+ }
|
|
|
+
|
|
|
+ WRT_REG_DWORD(®->ctrl_status,
|
|
|
+ CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
|
|
|
+ pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
|
|
|
+
|
|
|
+ udelay(100);
|
|
|
+ /* Wait for firmware to complete NVRAM accesses. */
|
|
|
+ mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
|
|
|
+ for (cnt = 10000 ; cnt && mb0; cnt--) {
|
|
|
+ udelay(5);
|
|
|
+ mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
|
|
|
+ barrier();
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Wait for soft-reset to complete. */
|
|
|
+ for (cnt = 0; cnt < 30000; cnt++) {
|
|
|
+ if ((RD_REG_DWORD(®->ctrl_status) &
|
|
|
+ CSRX_ISP_SOFT_RESET) == 0)
|
|
|
+ break;
|
|
|
+
|
|
|
+ udelay(10);
|
|
|
+ }
|
|
|
+ WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
|
|
|
+ RD_REG_DWORD(®->hccr); /* PCI Posting. */
|
|
|
+ }
|
|
|
+
|
|
|
+ for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
|
|
|
+ rval == QLA_SUCCESS; cnt--) {
|
|
|
+ if (cnt)
|
|
|
+ udelay(100);
|
|
|
+ else
|
|
|
+ rval = QLA_FUNCTION_TIMEOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (rval == QLA_SUCCESS)
|
|
|
+ rval = qla2xxx_dump_memory(ha, fw->code_ram,
|
|
|
+ sizeof(fw->code_ram), fw->ext_mem, &nxt);
|
|
|
+
|
|
|
+ if (rval == QLA_SUCCESS) {
|
|
|
+ nxt = qla2xxx_copy_queues(ha, nxt);
|
|
|
+ if (ha->eft)
|
|
|
+ memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
|
|
|
+ }
|
|
|
+
|
|
|
+ if (rval != QLA_SUCCESS) {
|
|
|
+ qla_printk(KERN_WARNING, ha,
|
|
|
+ "Failed to dump firmware (%x)!!!\n", rval);
|
|
|
+ ha->fw_dumped = 0;
|
|
|
|
|
|
} else {
|
|
|
qla_printk(KERN_INFO, ha,
|
|
@@ -1332,7 +2038,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
|
|
|
ha->fw_dumped = 1;
|
|
|
}
|
|
|
|
|
|
-qla24xx_fw_dump_failed:
|
|
|
+qla25xx_fw_dump_failed:
|
|
|
if (!hardware_locked)
|
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
|
}
|