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@@ -306,16 +306,22 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
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return true;
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}
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-static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
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+static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
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+ enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg = PIPESTAT(pipe);
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- u32 pipestat = I915_READ(reg) & 0x7fff0000;
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+ u32 pipestat = I915_READ(reg) & 0xffff0000;
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assert_spin_locked(&dev_priv->irq_lock);
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- I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
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- POSTING_READ(reg);
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+ if (enable) {
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+ I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
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+ POSTING_READ(reg);
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+ } else {
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+ if (pipestat & PIPE_FIFO_UNDERRUN_STATUS)
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+ DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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+ }
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}
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static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
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@@ -472,8 +478,8 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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intel_crtc->cpu_fifo_underrun_disabled = !enable;
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- if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
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- i9xx_clear_fifo_underrun(dev, pipe);
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+ if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
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+ i9xx_set_fifo_underrun_reporting(dev, pipe, enable);
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else if (IS_GEN5(dev) || IS_GEN6(dev))
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ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
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else if (IS_GEN7(dev))
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