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@@ -72,22 +72,24 @@
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/* Address definitions for the TCO */
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/* TCO base address */
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-#define TCOBASE (iTCO_wdt_private.tco_res->start)
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+#define TCOBASE(p) ((p)->tco_res->start)
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/* SMI Control and Enable Register */
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-#define SMI_EN (iTCO_wdt_private.smi_res->start)
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-
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-#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
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-#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
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-#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
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-#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
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-#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
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-#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
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-#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
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-#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
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-#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
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+#define SMI_EN(p) ((p)->smi_res->start)
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+
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+#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
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+#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
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+#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
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+#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
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+#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
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+#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
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+#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
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+#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
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+#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
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/* internal variables */
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-static struct { /* this is private data for the iTCO_wdt device */
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+struct iTCO_wdt_private {
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+ struct watchdog_device wddev;
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+
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/* TCO version/generation */
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unsigned int iTCO_version;
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struct resource *tco_res;
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@@ -100,12 +102,11 @@ static struct { /* this is private data for the iTCO_wdt device */
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unsigned long __iomem *gcs_pmc;
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/* the lock for io operations */
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spinlock_t io_lock;
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- struct platform_device *dev;
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/* the PCI-device */
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- struct pci_dev *pdev;
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+ struct pci_dev *pci_dev;
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/* whether or not the watchdog has been suspended */
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bool suspended;
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-} iTCO_wdt_private;
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+};
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/* module parameters */
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#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
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@@ -135,21 +136,23 @@ MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
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* every 0.6 seconds. v3's internal timer is stored as seconds (some
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* datasheets incorrectly state 0.6 seconds).
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*/
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-static inline unsigned int seconds_to_ticks(int secs)
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+static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
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+ int secs)
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{
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- return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6;
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+ return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
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}
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-static inline unsigned int ticks_to_seconds(int ticks)
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+static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
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+ int ticks)
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{
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- return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10;
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+ return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
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}
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-static inline u32 no_reboot_bit(void)
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+static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
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{
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u32 enable_bit;
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- switch (iTCO_wdt_private.iTCO_version) {
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+ switch (p->iTCO_version) {
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case 5:
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case 3:
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enable_bit = 0x00000010;
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@@ -167,40 +170,40 @@ static inline u32 no_reboot_bit(void)
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return enable_bit;
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}
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-static void iTCO_wdt_set_NO_REBOOT_bit(void)
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+static void iTCO_wdt_set_NO_REBOOT_bit(struct iTCO_wdt_private *p)
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{
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u32 val32;
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/* Set the NO_REBOOT bit: this disables reboots */
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- if (iTCO_wdt_private.iTCO_version >= 2) {
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- val32 = readl(iTCO_wdt_private.gcs_pmc);
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- val32 |= no_reboot_bit();
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- writel(val32, iTCO_wdt_private.gcs_pmc);
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- } else if (iTCO_wdt_private.iTCO_version == 1) {
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- pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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- val32 |= no_reboot_bit();
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- pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
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+ if (p->iTCO_version >= 2) {
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+ val32 = readl(p->gcs_pmc);
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+ val32 |= no_reboot_bit(p);
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+ writel(val32, p->gcs_pmc);
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+ } else if (p->iTCO_version == 1) {
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+ pci_read_config_dword(p->pci_dev, 0xd4, &val32);
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+ val32 |= no_reboot_bit(p);
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+ pci_write_config_dword(p->pci_dev, 0xd4, val32);
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}
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}
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-static int iTCO_wdt_unset_NO_REBOOT_bit(void)
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+static int iTCO_wdt_unset_NO_REBOOT_bit(struct iTCO_wdt_private *p)
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{
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- u32 enable_bit = no_reboot_bit();
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+ u32 enable_bit = no_reboot_bit(p);
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u32 val32 = 0;
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/* Unset the NO_REBOOT bit: this enables reboots */
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- if (iTCO_wdt_private.iTCO_version >= 2) {
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- val32 = readl(iTCO_wdt_private.gcs_pmc);
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+ if (p->iTCO_version >= 2) {
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+ val32 = readl(p->gcs_pmc);
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val32 &= ~enable_bit;
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- writel(val32, iTCO_wdt_private.gcs_pmc);
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+ writel(val32, p->gcs_pmc);
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- val32 = readl(iTCO_wdt_private.gcs_pmc);
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- } else if (iTCO_wdt_private.iTCO_version == 1) {
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- pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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+ val32 = readl(p->gcs_pmc);
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+ } else if (p->iTCO_version == 1) {
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+ pci_read_config_dword(p->pci_dev, 0xd4, &val32);
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val32 &= ~enable_bit;
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- pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
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+ pci_write_config_dword(p->pci_dev, 0xd4, val32);
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- pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
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+ pci_read_config_dword(p->pci_dev, 0xd4, &val32);
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}
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if (val32 & enable_bit)
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@@ -211,32 +214,33 @@ static int iTCO_wdt_unset_NO_REBOOT_bit(void)
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static int iTCO_wdt_start(struct watchdog_device *wd_dev)
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{
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+ struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
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unsigned int val;
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- spin_lock(&iTCO_wdt_private.io_lock);
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+ spin_lock(&p->io_lock);
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- iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
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+ iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
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/* disable chipset's NO_REBOOT bit */
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- if (iTCO_wdt_unset_NO_REBOOT_bit()) {
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ if (iTCO_wdt_unset_NO_REBOOT_bit(p)) {
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+ spin_unlock(&p->io_lock);
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pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
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return -EIO;
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}
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/* Force the timer to its reload value by writing to the TCO_RLD
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register */
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- if (iTCO_wdt_private.iTCO_version >= 2)
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- outw(0x01, TCO_RLD);
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- else if (iTCO_wdt_private.iTCO_version == 1)
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- outb(0x01, TCO_RLD);
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+ if (p->iTCO_version >= 2)
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+ outw(0x01, TCO_RLD(p));
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+ else if (p->iTCO_version == 1)
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+ outb(0x01, TCO_RLD(p));
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/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
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- val = inw(TCO1_CNT);
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+ val = inw(TCO1_CNT(p));
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val &= 0xf7ff;
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- outw(val, TCO1_CNT);
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- val = inw(TCO1_CNT);
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ outw(val, TCO1_CNT(p));
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+ val = inw(TCO1_CNT(p));
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+ spin_unlock(&p->io_lock);
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if (val & 0x0800)
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return -1;
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@@ -245,22 +249,23 @@ static int iTCO_wdt_start(struct watchdog_device *wd_dev)
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static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
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{
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+ struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
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unsigned int val;
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- spin_lock(&iTCO_wdt_private.io_lock);
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+ spin_lock(&p->io_lock);
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- iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
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+ iTCO_vendor_pre_stop(p->smi_res);
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/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
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- val = inw(TCO1_CNT);
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+ val = inw(TCO1_CNT(p));
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val |= 0x0800;
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- outw(val, TCO1_CNT);
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- val = inw(TCO1_CNT);
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+ outw(val, TCO1_CNT(p));
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+ val = inw(TCO1_CNT(p));
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/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
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- iTCO_wdt_set_NO_REBOOT_bit();
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+ iTCO_wdt_set_NO_REBOOT_bit(p);
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ spin_unlock(&p->io_lock);
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if ((val & 0x0800) == 0)
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return -1;
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@@ -269,67 +274,70 @@ static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
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static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
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{
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- spin_lock(&iTCO_wdt_private.io_lock);
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+ struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
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- iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
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+ spin_lock(&p->io_lock);
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+
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+ iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout);
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/* Reload the timer by writing to the TCO Timer Counter register */
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- if (iTCO_wdt_private.iTCO_version >= 2) {
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- outw(0x01, TCO_RLD);
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- } else if (iTCO_wdt_private.iTCO_version == 1) {
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+ if (p->iTCO_version >= 2) {
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+ outw(0x01, TCO_RLD(p));
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+ } else if (p->iTCO_version == 1) {
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/* Reset the timeout status bit so that the timer
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* needs to count down twice again before rebooting */
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- outw(0x0008, TCO1_STS); /* write 1 to clear bit */
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+ outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
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- outb(0x01, TCO_RLD);
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+ outb(0x01, TCO_RLD(p));
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}
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ spin_unlock(&p->io_lock);
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return 0;
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}
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static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
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{
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+ struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
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unsigned int val16;
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unsigned char val8;
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unsigned int tmrval;
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- tmrval = seconds_to_ticks(t);
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+ tmrval = seconds_to_ticks(p, t);
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/* For TCO v1 the timer counts down twice before rebooting */
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- if (iTCO_wdt_private.iTCO_version == 1)
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+ if (p->iTCO_version == 1)
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tmrval /= 2;
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/* from the specs: */
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/* "Values of 0h-3h are ignored and should not be attempted" */
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if (tmrval < 0x04)
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return -EINVAL;
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- if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) ||
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- ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
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+ if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
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+ (p->iTCO_version == 1 && tmrval > 0x03f))
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return -EINVAL;
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iTCO_vendor_pre_set_heartbeat(tmrval);
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/* Write new heartbeat to watchdog */
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- if (iTCO_wdt_private.iTCO_version >= 2) {
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- spin_lock(&iTCO_wdt_private.io_lock);
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- val16 = inw(TCOv2_TMR);
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+ if (p->iTCO_version >= 2) {
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+ spin_lock(&p->io_lock);
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+ val16 = inw(TCOv2_TMR(p));
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val16 &= 0xfc00;
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val16 |= tmrval;
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- outw(val16, TCOv2_TMR);
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- val16 = inw(TCOv2_TMR);
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ outw(val16, TCOv2_TMR(p));
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+ val16 = inw(TCOv2_TMR(p));
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+ spin_unlock(&p->io_lock);
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if ((val16 & 0x3ff) != tmrval)
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return -EINVAL;
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- } else if (iTCO_wdt_private.iTCO_version == 1) {
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- spin_lock(&iTCO_wdt_private.io_lock);
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- val8 = inb(TCOv1_TMR);
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+ } else if (p->iTCO_version == 1) {
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+ spin_lock(&p->io_lock);
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+ val8 = inb(TCOv1_TMR(p));
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val8 &= 0xc0;
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val8 |= (tmrval & 0xff);
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- outb(val8, TCOv1_TMR);
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- val8 = inb(TCOv1_TMR);
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ outb(val8, TCOv1_TMR(p));
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+ val8 = inb(TCOv1_TMR(p));
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+ spin_unlock(&p->io_lock);
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if ((val8 & 0x3f) != tmrval)
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return -EINVAL;
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@@ -341,27 +349,28 @@ static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
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static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
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{
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+ struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
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unsigned int val16;
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unsigned char val8;
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unsigned int time_left = 0;
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/* read the TCO Timer */
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- if (iTCO_wdt_private.iTCO_version >= 2) {
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- spin_lock(&iTCO_wdt_private.io_lock);
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- val16 = inw(TCO_RLD);
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+ if (p->iTCO_version >= 2) {
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+ spin_lock(&p->io_lock);
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+ val16 = inw(TCO_RLD(p));
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val16 &= 0x3ff;
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- spin_unlock(&iTCO_wdt_private.io_lock);
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+ spin_unlock(&p->io_lock);
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- time_left = ticks_to_seconds(val16);
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- } else if (iTCO_wdt_private.iTCO_version == 1) {
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- spin_lock(&iTCO_wdt_private.io_lock);
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- val8 = inb(TCO_RLD);
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+ time_left = ticks_to_seconds(p, val16);
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+ } else if (p->iTCO_version == 1) {
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+ spin_lock(&p->io_lock);
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|
|
+ val8 = inb(TCO_RLD(p));
|
|
|
val8 &= 0x3f;
|
|
|
- if (!(inw(TCO1_STS) & 0x0008))
|
|
|
- val8 += (inb(TCOv1_TMR) & 0x3f);
|
|
|
- spin_unlock(&iTCO_wdt_private.io_lock);
|
|
|
+ if (!(inw(TCO1_STS(p)) & 0x0008))
|
|
|
+ val8 += (inb(TCOv1_TMR(p)) & 0x3f);
|
|
|
+ spin_unlock(&p->io_lock);
|
|
|
|
|
|
- time_left = ticks_to_seconds(val8);
|
|
|
+ time_left = ticks_to_seconds(p, val8);
|
|
|
}
|
|
|
return time_left;
|
|
|
}
|
|
@@ -387,209 +396,152 @@ static const struct watchdog_ops iTCO_wdt_ops = {
|
|
|
.get_timeleft = iTCO_wdt_get_timeleft,
|
|
|
};
|
|
|
|
|
|
-static struct watchdog_device iTCO_wdt_watchdog_dev = {
|
|
|
- .info = &ident,
|
|
|
- .ops = &iTCO_wdt_ops,
|
|
|
-};
|
|
|
-
|
|
|
/*
|
|
|
* Init & exit routines
|
|
|
*/
|
|
|
|
|
|
-static void iTCO_wdt_cleanup(void)
|
|
|
-{
|
|
|
- /* Stop the timer before we leave */
|
|
|
- if (!nowayout)
|
|
|
- iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
|
|
|
-
|
|
|
- /* Deregister */
|
|
|
- watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
|
|
|
-
|
|
|
- /* release resources */
|
|
|
- release_region(iTCO_wdt_private.tco_res->start,
|
|
|
- resource_size(iTCO_wdt_private.tco_res));
|
|
|
- release_region(iTCO_wdt_private.smi_res->start,
|
|
|
- resource_size(iTCO_wdt_private.smi_res));
|
|
|
- if (iTCO_wdt_private.iTCO_version >= 2) {
|
|
|
- iounmap(iTCO_wdt_private.gcs_pmc);
|
|
|
- release_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
|
|
|
- resource_size(iTCO_wdt_private.gcs_pmc_res));
|
|
|
- }
|
|
|
-
|
|
|
- iTCO_wdt_private.tco_res = NULL;
|
|
|
- iTCO_wdt_private.smi_res = NULL;
|
|
|
- iTCO_wdt_private.gcs_pmc_res = NULL;
|
|
|
- iTCO_wdt_private.gcs_pmc = NULL;
|
|
|
-}
|
|
|
-
|
|
|
-static int iTCO_wdt_probe(struct platform_device *dev)
|
|
|
+static int iTCO_wdt_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
- int ret = -ENODEV;
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
|
|
|
+ struct iTCO_wdt_private *p;
|
|
|
unsigned long val32;
|
|
|
- struct itco_wdt_platform_data *pdata = dev_get_platdata(&dev->dev);
|
|
|
+ int ret;
|
|
|
|
|
|
if (!pdata)
|
|
|
- goto out;
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
|
|
|
+ if (!p)
|
|
|
+ return -ENOMEM;
|
|
|
|
|
|
- spin_lock_init(&iTCO_wdt_private.io_lock);
|
|
|
+ spin_lock_init(&p->io_lock);
|
|
|
|
|
|
- iTCO_wdt_private.tco_res =
|
|
|
- platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
|
|
|
- if (!iTCO_wdt_private.tco_res)
|
|
|
- goto out;
|
|
|
+ p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
|
|
|
+ if (!p->tco_res)
|
|
|
+ return -ENODEV;
|
|
|
|
|
|
- iTCO_wdt_private.smi_res =
|
|
|
- platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
|
|
|
- if (!iTCO_wdt_private.smi_res)
|
|
|
- goto out;
|
|
|
+ p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
|
|
|
+ if (!p->smi_res)
|
|
|
+ return -ENODEV;
|
|
|
|
|
|
- iTCO_wdt_private.iTCO_version = pdata->version;
|
|
|
- iTCO_wdt_private.dev = dev;
|
|
|
- iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
|
|
|
+ p->iTCO_version = pdata->version;
|
|
|
+ p->pci_dev = to_pci_dev(dev->parent);
|
|
|
|
|
|
/*
|
|
|
* Get the Memory-Mapped GCS or PMC register, we need it for the
|
|
|
* NO_REBOOT flag (TCO v2 and v3).
|
|
|
*/
|
|
|
- if (iTCO_wdt_private.iTCO_version >= 2) {
|
|
|
- iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev,
|
|
|
- IORESOURCE_MEM,
|
|
|
- ICH_RES_MEM_GCS_PMC);
|
|
|
-
|
|
|
- if (!iTCO_wdt_private.gcs_pmc_res)
|
|
|
- goto out;
|
|
|
-
|
|
|
- if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
|
|
|
- resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) {
|
|
|
- ret = -EBUSY;
|
|
|
- goto out;
|
|
|
- }
|
|
|
- iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start,
|
|
|
- resource_size(iTCO_wdt_private.gcs_pmc_res));
|
|
|
- if (!iTCO_wdt_private.gcs_pmc) {
|
|
|
- ret = -EIO;
|
|
|
- goto unreg_gcs_pmc;
|
|
|
- }
|
|
|
+ if (p->iTCO_version >= 2) {
|
|
|
+ p->gcs_pmc_res = platform_get_resource(pdev,
|
|
|
+ IORESOURCE_MEM,
|
|
|
+ ICH_RES_MEM_GCS_PMC);
|
|
|
+ p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
|
|
|
+ if (IS_ERR(p->gcs_pmc))
|
|
|
+ return PTR_ERR(p->gcs_pmc);
|
|
|
}
|
|
|
|
|
|
/* Check chipset's NO_REBOOT bit */
|
|
|
- if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
|
|
|
+ if (iTCO_wdt_unset_NO_REBOOT_bit(p) &&
|
|
|
+ iTCO_vendor_check_noreboot_on()) {
|
|
|
pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
|
|
|
- ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
|
|
|
- goto unmap_gcs_pmc;
|
|
|
+ return -ENODEV; /* Cannot reset NO_REBOOT bit */
|
|
|
}
|
|
|
|
|
|
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
|
|
|
- iTCO_wdt_set_NO_REBOOT_bit();
|
|
|
+ iTCO_wdt_set_NO_REBOOT_bit(p);
|
|
|
|
|
|
/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
|
|
|
- if (!request_region(iTCO_wdt_private.smi_res->start,
|
|
|
- resource_size(iTCO_wdt_private.smi_res), dev->name)) {
|
|
|
+ if (!devm_request_region(dev, p->smi_res->start,
|
|
|
+ resource_size(p->smi_res),
|
|
|
+ pdev->name)) {
|
|
|
pr_err("I/O address 0x%04llx already in use, device disabled\n",
|
|
|
- (u64)SMI_EN);
|
|
|
- ret = -EBUSY;
|
|
|
- goto unmap_gcs_pmc;
|
|
|
+ (u64)SMI_EN(p));
|
|
|
+ return -EBUSY;
|
|
|
}
|
|
|
- if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
|
|
|
+ if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
|
|
|
/*
|
|
|
* Bit 13: TCO_EN -> 0
|
|
|
* Disables TCO logic generating an SMI#
|
|
|
*/
|
|
|
- val32 = inl(SMI_EN);
|
|
|
+ val32 = inl(SMI_EN(p));
|
|
|
val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
|
|
|
- outl(val32, SMI_EN);
|
|
|
+ outl(val32, SMI_EN(p));
|
|
|
}
|
|
|
|
|
|
- if (!request_region(iTCO_wdt_private.tco_res->start,
|
|
|
- resource_size(iTCO_wdt_private.tco_res), dev->name)) {
|
|
|
+ if (!devm_request_region(dev, p->tco_res->start,
|
|
|
+ resource_size(p->tco_res),
|
|
|
+ pdev->name)) {
|
|
|
pr_err("I/O address 0x%04llx already in use, device disabled\n",
|
|
|
- (u64)TCOBASE);
|
|
|
- ret = -EBUSY;
|
|
|
- goto unreg_smi;
|
|
|
+ (u64)TCOBASE(p));
|
|
|
+ return -EBUSY;
|
|
|
}
|
|
|
|
|
|
pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
|
|
|
- pdata->name, pdata->version, (u64)TCOBASE);
|
|
|
+ pdata->name, pdata->version, (u64)TCOBASE(p));
|
|
|
|
|
|
/* Clear out the (probably old) status */
|
|
|
- switch (iTCO_wdt_private.iTCO_version) {
|
|
|
+ switch (p->iTCO_version) {
|
|
|
case 5:
|
|
|
case 4:
|
|
|
- outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
|
|
|
- outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
|
|
|
+ outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
|
|
|
+ outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
|
|
|
break;
|
|
|
case 3:
|
|
|
- outl(0x20008, TCO1_STS);
|
|
|
+ outl(0x20008, TCO1_STS(p));
|
|
|
break;
|
|
|
case 2:
|
|
|
case 1:
|
|
|
default:
|
|
|
- outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
|
|
|
- outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
|
|
|
- outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
|
|
|
+ outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
|
|
|
+ outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
|
|
|
+ outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
- iTCO_wdt_watchdog_dev.bootstatus = 0;
|
|
|
- iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
|
|
|
- watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
|
|
|
- iTCO_wdt_watchdog_dev.parent = &dev->dev;
|
|
|
+ p->wddev.info = &ident,
|
|
|
+ p->wddev.ops = &iTCO_wdt_ops,
|
|
|
+ p->wddev.bootstatus = 0;
|
|
|
+ p->wddev.timeout = WATCHDOG_TIMEOUT;
|
|
|
+ watchdog_set_nowayout(&p->wddev, nowayout);
|
|
|
+ p->wddev.parent = dev;
|
|
|
+
|
|
|
+ watchdog_set_drvdata(&p->wddev, p);
|
|
|
+ platform_set_drvdata(pdev, p);
|
|
|
|
|
|
/* Make sure the watchdog is not running */
|
|
|
- iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
|
|
|
+ iTCO_wdt_stop(&p->wddev);
|
|
|
|
|
|
/* Check that the heartbeat value is within it's range;
|
|
|
if not reset to the default */
|
|
|
- if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
|
|
|
- iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
|
|
|
+ if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
|
|
|
+ iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
|
|
|
pr_info("timeout value out of range, using %d\n",
|
|
|
WATCHDOG_TIMEOUT);
|
|
|
}
|
|
|
|
|
|
- ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
|
|
|
+ watchdog_stop_on_reboot(&p->wddev);
|
|
|
+ ret = devm_watchdog_register_device(dev, &p->wddev);
|
|
|
if (ret != 0) {
|
|
|
pr_err("cannot register watchdog device (err=%d)\n", ret);
|
|
|
- goto unreg_tco;
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
|
|
|
heartbeat, nowayout);
|
|
|
|
|
|
return 0;
|
|
|
-
|
|
|
-unreg_tco:
|
|
|
- release_region(iTCO_wdt_private.tco_res->start,
|
|
|
- resource_size(iTCO_wdt_private.tco_res));
|
|
|
-unreg_smi:
|
|
|
- release_region(iTCO_wdt_private.smi_res->start,
|
|
|
- resource_size(iTCO_wdt_private.smi_res));
|
|
|
-unmap_gcs_pmc:
|
|
|
- if (iTCO_wdt_private.iTCO_version >= 2)
|
|
|
- iounmap(iTCO_wdt_private.gcs_pmc);
|
|
|
-unreg_gcs_pmc:
|
|
|
- if (iTCO_wdt_private.iTCO_version >= 2)
|
|
|
- release_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
|
|
|
- resource_size(iTCO_wdt_private.gcs_pmc_res));
|
|
|
-out:
|
|
|
- iTCO_wdt_private.tco_res = NULL;
|
|
|
- iTCO_wdt_private.smi_res = NULL;
|
|
|
- iTCO_wdt_private.gcs_pmc_res = NULL;
|
|
|
- iTCO_wdt_private.gcs_pmc = NULL;
|
|
|
-
|
|
|
- return ret;
|
|
|
}
|
|
|
|
|
|
-static int iTCO_wdt_remove(struct platform_device *dev)
|
|
|
+static int iTCO_wdt_remove(struct platform_device *pdev)
|
|
|
{
|
|
|
- if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
|
|
|
- iTCO_wdt_cleanup();
|
|
|
+ struct iTCO_wdt_private *p = platform_get_drvdata(pdev);
|
|
|
|
|
|
- return 0;
|
|
|
-}
|
|
|
+ /* Stop the timer before we leave */
|
|
|
+ if (!nowayout)
|
|
|
+ iTCO_wdt_stop(&p->wddev);
|
|
|
|
|
|
-static void iTCO_wdt_shutdown(struct platform_device *dev)
|
|
|
-{
|
|
|
- iTCO_wdt_stop(NULL);
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
@@ -610,21 +562,24 @@ static inline bool need_suspend(void) { return true; }
|
|
|
|
|
|
static int iTCO_wdt_suspend_noirq(struct device *dev)
|
|
|
{
|
|
|
+ struct iTCO_wdt_private *p = dev_get_drvdata(dev);
|
|
|
int ret = 0;
|
|
|
|
|
|
- iTCO_wdt_private.suspended = false;
|
|
|
- if (watchdog_active(&iTCO_wdt_watchdog_dev) && need_suspend()) {
|
|
|
- ret = iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
|
|
|
+ p->suspended = false;
|
|
|
+ if (watchdog_active(&p->wddev) && need_suspend()) {
|
|
|
+ ret = iTCO_wdt_stop(&p->wddev);
|
|
|
if (!ret)
|
|
|
- iTCO_wdt_private.suspended = true;
|
|
|
+ p->suspended = true;
|
|
|
}
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
static int iTCO_wdt_resume_noirq(struct device *dev)
|
|
|
{
|
|
|
- if (iTCO_wdt_private.suspended)
|
|
|
- iTCO_wdt_start(&iTCO_wdt_watchdog_dev);
|
|
|
+ struct iTCO_wdt_private *p = dev_get_drvdata(dev);
|
|
|
+
|
|
|
+ if (p->suspended)
|
|
|
+ iTCO_wdt_start(&p->wddev);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
@@ -642,7 +597,6 @@ static const struct dev_pm_ops iTCO_wdt_pm = {
|
|
|
static struct platform_driver iTCO_wdt_driver = {
|
|
|
.probe = iTCO_wdt_probe,
|
|
|
.remove = iTCO_wdt_remove,
|
|
|
- .shutdown = iTCO_wdt_shutdown,
|
|
|
.driver = {
|
|
|
.name = DRV_NAME,
|
|
|
.pm = ITCO_WDT_PM_OPS,
|
|
@@ -651,15 +605,9 @@ static struct platform_driver iTCO_wdt_driver = {
|
|
|
|
|
|
static int __init iTCO_wdt_init_module(void)
|
|
|
{
|
|
|
- int err;
|
|
|
-
|
|
|
pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
|
|
|
|
|
|
- err = platform_driver_register(&iTCO_wdt_driver);
|
|
|
- if (err)
|
|
|
- return err;
|
|
|
-
|
|
|
- return 0;
|
|
|
+ return platform_driver_register(&iTCO_wdt_driver);
|
|
|
}
|
|
|
|
|
|
static void __exit iTCO_wdt_cleanup_module(void)
|