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@@ -466,11 +466,13 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
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* could happen that GuC sets the bit for 2nd interrupt but Host
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* clears out the bit on handling the 1st interrupt.
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*/
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+ disable_rpm_wakeref_asserts(dev_priv);
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spin_lock(&guc->irq_lock);
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val = I915_READ(SOFT_SCRATCH(15));
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msg = val & guc->msg_enabled_mask;
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I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
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spin_unlock(&guc->irq_lock);
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+ enable_rpm_wakeref_asserts(dev_priv);
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intel_guc_to_host_process_recv_msg(guc, msg);
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}
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