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@@ -2071,13 +2071,23 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
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addr = page_address(tce_mem);
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memset(addr, 0, tce_table_size);
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+ /* Setup linux iommu table */
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+ pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
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+ IOMMU_PAGE_SHIFT_4K);
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+
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+ tbl->it_ops = &pnv_ioda2_iommu_ops;
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+ iommu_init_table(tbl, phb->hose->node);
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+#ifdef CONFIG_IOMMU_API
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+ pe->table_group.ops = &pnv_pci_ioda2_ops;
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+#endif
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+
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/*
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* Map TCE table through TVT. The TVE index is the PE number
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* shifted by 1 bit for 32-bits DMA space.
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*/
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rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
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- pe->pe_number << 1, 1, __pa(addr),
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- tce_table_size, 0x1000);
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+ pe->pe_number << 1, 1, __pa(tbl->it_base),
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+ tbl->it_size << 3, 1ULL << tbl->it_page_shift);
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if (rc) {
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pe_err(pe, "Failed to configure 32-bit TCE table,"
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" err %ld\n", rc);
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@@ -2086,20 +2096,10 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
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pnv_pci_ioda2_tce_invalidate_entire(pe);
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- /* Setup linux iommu table */
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- pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
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- IOMMU_PAGE_SHIFT_4K);
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-
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/* OPAL variant of PHB3 invalidated TCEs */
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if (phb->ioda.tce_inval_reg)
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tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
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- tbl->it_ops = &pnv_ioda2_iommu_ops;
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- iommu_init_table(tbl, phb->hose->node);
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-#ifdef CONFIG_IOMMU_API
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- pe->table_group.ops = &pnv_pci_ioda2_ops;
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-#endif
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-
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if (pe->flags & PNV_IODA_PE_DEV) {
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/*
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* Setting table base here only for carrying iommu_group
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