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@@ -1193,9 +1193,8 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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pipe);
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enum intel_display_power_domain power_domain;
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- /* if we need the pipe quirk it must be always on */
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- if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
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- (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
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+ /* we keep both pipes enabled on 830 */
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+ if (IS_I830(dev_priv))
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state = true;
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power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
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@@ -1629,8 +1628,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
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}
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/* Don't disable pipe or pipe PLLs if needed */
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- if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
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- (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
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+ if (IS_I830(dev_priv))
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return;
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/* Make sure the pipe isn't still relying on us */
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@@ -1913,8 +1911,8 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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reg = PIPECONF(cpu_transcoder);
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val = I915_READ(reg);
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if (val & PIPECONF_ENABLE) {
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- WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
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- (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
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+ /* we keep both pipes enabled on 830 */
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+ WARN_ON(!IS_I830(dev_priv));
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return;
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}
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@@ -1974,8 +1972,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
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val &= ~PIPECONF_DOUBLE_WIDE;
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/* Don't disable pipe or pipe PLLs if needed */
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- if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
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- !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
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+ if (!IS_I830(dev_priv))
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val &= ~PIPECONF_ENABLE;
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I915_WRITE(reg, val);
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@@ -7045,8 +7042,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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pipeconf = 0;
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- if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
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- (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
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+ /* we keep both pipes enabled on 830 */
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+ if (IS_I830(dev_priv))
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pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
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if (intel_crtc->config->double_wide)
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@@ -12231,9 +12228,8 @@ verify_crtc_state(struct drm_crtc *crtc,
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active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
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- /* hw state is inconsistent with the pipe quirk */
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- if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
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- (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
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+ /* we keep both pipes enabled on 830 */
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+ if (IS_I830(dev_priv))
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active = new_crtc_state->active;
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I915_STATE_WARN(new_crtc_state->active != active,
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@@ -14731,27 +14727,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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}
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}
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-/*
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- * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
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- * resume, or other times. This quirk makes sure that's the case for
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- * affected systems.
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- */
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-static void quirk_pipea_force(struct drm_device *dev)
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-{
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- struct drm_i915_private *dev_priv = to_i915(dev);
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-
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- dev_priv->quirks |= QUIRK_PIPEA_FORCE;
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- DRM_INFO("applying pipe a force quirk\n");
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-}
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-
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-static void quirk_pipeb_force(struct drm_device *dev)
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-{
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- struct drm_i915_private *dev_priv = to_i915(dev);
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-
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- dev_priv->quirks |= QUIRK_PIPEB_FORCE;
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- DRM_INFO("applying pipe b force quirk\n");
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-}
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-
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/*
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* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
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*/
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@@ -14817,12 +14792,6 @@ static const struct intel_dmi_quirk intel_dmi_quirks[] = {
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};
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static struct intel_quirk intel_quirks[] = {
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- /* 830 needs to leave pipe A & dpll A up */
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- { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
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-
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- /* 830 needs to leave pipe B & dpll B up */
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- { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
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-
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/* Lenovo U160 cannot use SSC on LVDS */
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{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
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@@ -15228,37 +15197,6 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
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POSTING_READ(DPLL(pipe));
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}
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-static void intel_enable_pipe_a(struct drm_device *dev,
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- struct drm_modeset_acquire_ctx *ctx)
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-{
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- struct intel_connector *connector;
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- struct drm_connector_list_iter conn_iter;
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- struct drm_connector *crt = NULL;
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- struct intel_load_detect_pipe load_detect_temp;
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- int ret;
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-
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- /* We can't just switch on the pipe A, we need to set things up with a
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- * proper mode and output configuration. As a gross hack, enable pipe A
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- * by enabling the load detect pipe once. */
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- drm_connector_list_iter_begin(dev, &conn_iter);
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- for_each_intel_connector_iter(connector, &conn_iter) {
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- if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
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- crt = &connector->base;
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- break;
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- }
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- }
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- drm_connector_list_iter_end(&conn_iter);
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-
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- if (!crt)
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- return;
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-
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- ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
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- WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
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-
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- if (ret > 0)
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- intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
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-}
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-
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static bool
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intel_check_plane_mapping(struct intel_crtc *crtc)
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{
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@@ -15357,16 +15295,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
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crtc->plane = plane;
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}
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- if (!IS_I830(dev_priv) &&
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- dev_priv->quirks & QUIRK_PIPEA_FORCE &&
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- crtc->pipe == PIPE_A && !crtc->active) {
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- /* BIOS forgot to enable pipe A, this mostly happens after
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- * resume. Force-enable the pipe to fix this, the update_dpms
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- * call below we restore the pipe to the right state, but leave
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- * the required bits on. */
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- intel_enable_pipe_a(dev, ctx);
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- }
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-
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/* Adjust the state of the output pipe according to whether we
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* have active connectors/encoders. */
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if (crtc->active && !intel_crtc_has_encoders(crtc))
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