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+/*
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+ * Copyright 2008 Advanced Micro Devices, Inc.
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+ * Copyright 2008 Red Hat Inc.
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+ * Copyright 2009 Christian König.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Christian König
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+ * Rafał Miłecki
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+ */
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+#include "drmP.h"
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+#include "radeon_drm.h"
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+#include "radeon.h"
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+#include "radeon_asic.h"
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+#include "evergreend.h"
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+#include "atom.h"
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+
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+/*
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+ * update the N and CTS parameters for a given pixel clock rate
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+ */
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+static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
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+{
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+ struct drm_device *dev = encoder->dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
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+ uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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+
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+ WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
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+ WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
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+
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+ WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
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+ WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
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+
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+ WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
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+ WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
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+}
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+
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+/*
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+ * calculate the crc for a given info frame
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+ */
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+static void evergreen_hdmi_infoframe_checksum(uint8_t packetType,
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+ uint8_t versionNumber,
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+ uint8_t length,
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+ uint8_t *frame)
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+{
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+ int i;
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+ frame[0] = packetType + versionNumber + length;
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+ for (i = 1; i <= length; i++)
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+ frame[0] += frame[i];
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+ frame[0] = 0x100 - frame[0];
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+}
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+
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+/*
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+ * build a HDMI Video Info Frame
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+ */
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+static void evergreen_hdmi_videoinfoframe(
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+ struct drm_encoder *encoder,
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+ uint8_t color_format,
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+ int active_information_present,
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+ uint8_t active_format_aspect_ratio,
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+ uint8_t scan_information,
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+ uint8_t colorimetry,
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+ uint8_t ex_colorimetry,
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+ uint8_t quantization,
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+ int ITC,
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+ uint8_t picture_aspect_ratio,
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+ uint8_t video_format_identification,
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+ uint8_t pixel_repetition,
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+ uint8_t non_uniform_picture_scaling,
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+ uint8_t bar_info_data_valid,
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+ uint16_t top_bar,
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+ uint16_t bottom_bar,
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+ uint16_t left_bar,
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+ uint16_t right_bar
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+)
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+{
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+ struct drm_device *dev = encoder->dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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+
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+ uint8_t frame[14];
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+
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+ frame[0x0] = 0;
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+ frame[0x1] =
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+ (scan_information & 0x3) |
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+ ((bar_info_data_valid & 0x3) << 2) |
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+ ((active_information_present & 0x1) << 4) |
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+ ((color_format & 0x3) << 5);
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+ frame[0x2] =
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+ (active_format_aspect_ratio & 0xF) |
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+ ((picture_aspect_ratio & 0x3) << 4) |
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+ ((colorimetry & 0x3) << 6);
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+ frame[0x3] =
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+ (non_uniform_picture_scaling & 0x3) |
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+ ((quantization & 0x3) << 2) |
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+ ((ex_colorimetry & 0x7) << 4) |
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+ ((ITC & 0x1) << 7);
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+ frame[0x4] = (video_format_identification & 0x7F);
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+ frame[0x5] = (pixel_repetition & 0xF);
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+ frame[0x6] = (top_bar & 0xFF);
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+ frame[0x7] = (top_bar >> 8);
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+ frame[0x8] = (bottom_bar & 0xFF);
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+ frame[0x9] = (bottom_bar >> 8);
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+ frame[0xA] = (left_bar & 0xFF);
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+ frame[0xB] = (left_bar >> 8);
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+ frame[0xC] = (right_bar & 0xFF);
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+ frame[0xD] = (right_bar >> 8);
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+
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+ evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
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+ /* Our header values (type, version, length) should be alright, Intel
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+ * is using the same. Checksum function also seems to be OK, it works
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+ * fine for audio infoframe. However calculated value is always lower
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+ * by 2 in comparison to fglrx. It breaks displaying anything in case
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+ * of TVs that strictly check the checksum. Hack it manually here to
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+ * workaround this issue. */
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+ frame[0x0] += 2;
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+
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+ WREG32(AFMT_AVI_INFO0 + offset,
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+ frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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+ WREG32(AFMT_AVI_INFO1 + offset,
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+ frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
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+ WREG32(AFMT_AVI_INFO2 + offset,
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+ frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
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+ WREG32(AFMT_AVI_INFO3 + offset,
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+ frame[0xC] | (frame[0xD] << 8));
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+}
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+
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+/*
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+ * update the info frames with the data from the current display mode
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+ */
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+void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
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+{
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+ struct drm_device *dev = encoder->dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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+
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+ if (ASIC_IS_DCE5(rdev))
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+ return;
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+
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+ if (!to_radeon_encoder(encoder)->hdmi_enabled)
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+ return;
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+
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+ r600_audio_set_clock(encoder, mode->clock);
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+
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+ WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
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+ WREG32(HDMI_GC + offset, 0x0);
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+
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+ /* Send audio packets */
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+ WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,
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+ AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);
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+
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+ WREG32(HDMI_ACR_PACKET_CONTROL + offset, 0x1000);
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+
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+ evergreen_hdmi_update_ACR(encoder, mode->clock);
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+
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+ WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 0x13);
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+
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+ WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 0x202);
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+
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+ evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0);
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+
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+ /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
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+ WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
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+ WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
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+ WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
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+ WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
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+
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+ /* audio packets per line, does anyone know how to calc this ? */
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+ WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000);
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+}
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Rafał Miłecki