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@@ -201,6 +201,19 @@ static const struct ce_pipe_config target_ce_config_wlan[] = {
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/* CE7 used only by Host */
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/* CE7 used only by Host */
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};
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};
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+static bool ath10k_pci_irq_pending(struct ath10k *ar)
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+{
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+ u32 cause;
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+
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+ /* Check if the shared legacy irq is for us */
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+ cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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+ PCIE_INTR_CAUSE_ADDRESS);
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+ if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
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+ return true;
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+
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+ return false;
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+}
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+
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/*
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/*
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* Diagnostic read/write access is provided for startup/config/debug usage.
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* Diagnostic read/write access is provided for startup/config/debug usage.
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* Caller must guarantee proper alignment, when applicable, and single user
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* Caller must guarantee proper alignment, when applicable, and single user
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@@ -2086,6 +2099,9 @@ static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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if (ar_pci->num_msi_intrs == 0) {
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if (ar_pci->num_msi_intrs == 0) {
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+ if (!ath10k_pci_irq_pending(ar))
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+ return IRQ_NONE;
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+
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/*
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/*
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* IMPORTANT: INTR_CLR regiser has to be set after
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* IMPORTANT: INTR_CLR regiser has to be set after
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* INTR_ENABLE is set to 0, otherwise interrupt can not be
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* INTR_ENABLE is set to 0, otherwise interrupt can not be
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