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@@ -39,6 +39,9 @@
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#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
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#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
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#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
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#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
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#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
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#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
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+#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
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+#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
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+#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
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/* AMD-specific bits */
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/* AMD-specific bits */
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#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
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#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
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