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@@ -36,21 +36,22 @@
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* How the whole thing works (courtesy of Christoffer Dall):
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*
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* - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
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- * something is pending
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- * - VGIC pending interrupts are stored on the vgic.irq_state vgic
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- * bitmap (this bitmap is updated by both user land ioctls and guest
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- * mmio ops, and other in-kernel peripherals such as the
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- * arch. timers) and indicate the 'wire' state.
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+ * something is pending on the CPU interface.
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+ * - Interrupts that are pending on the distributor are stored on the
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+ * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
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+ * ioctls and guest mmio ops, and other in-kernel peripherals such as the
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+ * arch. timers).
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* - Every time the bitmap changes, the irq_pending_on_cpu oracle is
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* recalculated
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* - To calculate the oracle, we need info for each cpu from
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* compute_pending_for_cpu, which considers:
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- * - PPI: dist->irq_state & dist->irq_enable
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- * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
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- * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
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+ * - PPI: dist->irq_pending & dist->irq_enable
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+ * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
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+ * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
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* registers, stored on each vcpu. We only keep one bit of
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* information per interrupt, making sure that only one vcpu can
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* accept the interrupt.
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+ * - If any of the above state changes, we must recalculate the oracle.
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* - The same is true when injecting an interrupt, except that we only
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* consider a single interrupt at a time. The irq_spi_cpu array
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* contains the target CPU for each SPI.
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@@ -60,13 +61,18 @@
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* the 'line' again. This is achieved as such:
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*
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* - When a level interrupt is moved onto a vcpu, the corresponding
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- * bit in irq_active is set. As long as this bit is set, the line
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+ * bit in irq_queued is set. As long as this bit is set, the line
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* will be ignored for further interrupts. The interrupt is injected
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* into the vcpu with the GICH_LR_EOI bit set (generate a
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* maintenance interrupt on EOI).
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* - When the interrupt is EOIed, the maintenance interrupt fires,
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- * and clears the corresponding bit in irq_active. This allow the
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+ * and clears the corresponding bit in irq_queued. This allows the
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* interrupt line to be sampled again.
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+ * - Note that level-triggered interrupts can also be set to pending from
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+ * writes to GICD_ISPENDRn and lowering the external input line does not
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+ * cause the interrupt to become inactive in such a situation.
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+ * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
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+ * inactive as long as the external input line is held high.
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*/
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#define VGIC_ADDR_UNDEF (-1)
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@@ -89,6 +95,7 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
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static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
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static void vgic_update_state(struct kvm *kvm);
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static void vgic_kick_vcpus(struct kvm *kvm);
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+static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi);
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static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
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static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
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static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
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@@ -99,10 +106,8 @@ static const struct vgic_ops *vgic_ops;
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static const struct vgic_params *vgic;
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/*
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- * struct vgic_bitmap contains unions that provide two views of
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- * the same data. In one case it is an array of registers of
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- * u32's, and in the other case it is a bitmap of unsigned
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- * longs.
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+ * struct vgic_bitmap contains a bitmap made of unsigned longs, but
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+ * extracts u32s out of them.
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*
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* This does not work on 64-bit BE systems, because the bitmap access
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* will store two consecutive 32-bit words with the higher-addressed
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@@ -118,23 +123,45 @@ static const struct vgic_params *vgic;
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#define REG_OFFSET_SWIZZLE 0
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#endif
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+static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs)
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+{
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+ int nr_longs;
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+
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+ nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS);
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+
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+ b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL);
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+ if (!b->private)
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+ return -ENOMEM;
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+
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+ b->shared = b->private + nr_cpus;
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+
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+ return 0;
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+}
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+
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+static void vgic_free_bitmap(struct vgic_bitmap *b)
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+{
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+ kfree(b->private);
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+ b->private = NULL;
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+ b->shared = NULL;
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+}
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+
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static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
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int cpuid, u32 offset)
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{
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offset >>= 2;
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if (!offset)
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- return x->percpu[cpuid].reg + (offset ^ REG_OFFSET_SWIZZLE);
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+ return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE;
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else
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- return x->shared.reg + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
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+ return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
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}
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static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
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int cpuid, int irq)
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{
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if (irq < VGIC_NR_PRIVATE_IRQS)
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- return test_bit(irq, x->percpu[cpuid].reg_ul);
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+ return test_bit(irq, x->private + cpuid);
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- return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
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+ return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared);
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}
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static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
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@@ -143,9 +170,9 @@ static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
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unsigned long *reg;
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if (irq < VGIC_NR_PRIVATE_IRQS) {
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- reg = x->percpu[cpuid].reg_ul;
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+ reg = x->private + cpuid;
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} else {
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- reg = x->shared.reg_ul;
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+ reg = x->shared;
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irq -= VGIC_NR_PRIVATE_IRQS;
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}
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@@ -157,24 +184,49 @@ static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
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static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
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{
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- if (unlikely(cpuid >= VGIC_MAX_CPUS))
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- return NULL;
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- return x->percpu[cpuid].reg_ul;
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+ return x->private + cpuid;
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}
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static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
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{
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- return x->shared.reg_ul;
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+ return x->shared;
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+}
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+
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+static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs)
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+{
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+ int size;
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+
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+ size = nr_cpus * VGIC_NR_PRIVATE_IRQS;
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+ size += nr_irqs - VGIC_NR_PRIVATE_IRQS;
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+
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+ x->private = kzalloc(size, GFP_KERNEL);
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+ if (!x->private)
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+ return -ENOMEM;
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+
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+ x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32);
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+ return 0;
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+}
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+
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+static void vgic_free_bytemap(struct vgic_bytemap *b)
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+{
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+ kfree(b->private);
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+ b->private = NULL;
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+ b->shared = NULL;
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}
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static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
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{
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- offset >>= 2;
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- BUG_ON(offset > (VGIC_NR_IRQS / 4));
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- if (offset < 8)
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- return x->percpu[cpuid] + offset;
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- else
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- return x->shared + offset - 8;
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+ u32 *reg;
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+
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+ if (offset < VGIC_NR_PRIVATE_IRQS) {
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+ reg = x->private;
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+ offset += cpuid * VGIC_NR_PRIVATE_IRQS;
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+ } else {
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+ reg = x->shared;
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+ offset -= VGIC_NR_PRIVATE_IRQS;
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+ }
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+
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+ return reg + (offset / sizeof(u32));
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}
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#define VGIC_CFG_LEVEL 0
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@@ -196,46 +248,81 @@ static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
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return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
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}
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-static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
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+static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq)
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+{
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+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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+
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+ return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq);
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+}
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+
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+static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq)
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+{
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+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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+
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+ vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1);
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+}
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+
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+static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq)
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+{
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+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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+
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+ vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0);
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+}
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+
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+static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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- return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
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+ return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq);
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}
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-static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
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+static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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- vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
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+ vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1);
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}
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-static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
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+static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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- vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
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+ vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0);
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+}
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+
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+static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq)
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+{
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+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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+
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+ return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq);
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+}
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+
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+static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq)
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+{
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+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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+
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+ vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0);
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}
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static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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- return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
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+ return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq);
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}
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-static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
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+static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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- vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
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+ vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1);
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}
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-static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
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+static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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- vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
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+ vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0);
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}
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static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
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@@ -256,6 +343,11 @@ static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
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vcpu->arch.vgic_cpu.pending_shared);
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}
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+static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq)
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+{
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+ return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq);
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+}
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+
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static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
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{
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return le32_to_cpu(*((u32 *)mmio->data)) & mask;
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@@ -347,7 +439,7 @@ static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
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case 4: /* GICD_TYPER */
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reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
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- reg |= (VGIC_NR_IRQS >> 5) - 1;
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+ reg |= (vcpu->kvm->arch.vgic.nr_irqs >> 5) - 1;
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vgic_reg_access(mmio, ®, word_offset,
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ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
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break;
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@@ -409,11 +501,33 @@ static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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{
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- u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
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- vcpu->vcpu_id, offset);
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+ u32 *reg, orig;
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+ u32 level_mask;
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+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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+
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+ reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset);
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+ level_mask = (~(*reg));
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+
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+ /* Mark both level and edge triggered irqs as pending */
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+ reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
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+ orig = *reg;
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vgic_reg_access(mmio, reg, offset,
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ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
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+
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if (mmio->is_write) {
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+ /* Set the soft-pending flag only for level-triggered irqs */
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+ reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
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+ vcpu->vcpu_id, offset);
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+ vgic_reg_access(mmio, reg, offset,
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+ ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
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+ *reg &= level_mask;
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+
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+ /* Ignore writes to SGIs */
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+ if (offset < 2) {
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+ *reg &= ~0xffff;
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+ *reg |= orig & 0xffff;
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+ }
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+
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vgic_update_state(vcpu->kvm);
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return true;
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}
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@@ -425,11 +539,34 @@ static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
|
|
|
phys_addr_t offset)
|
|
|
{
|
|
|
- u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
|
|
|
- vcpu->vcpu_id, offset);
|
|
|
+ u32 *level_active;
|
|
|
+ u32 *reg, orig;
|
|
|
+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
|
|
+
|
|
|
+ reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
|
|
|
+ orig = *reg;
|
|
|
vgic_reg_access(mmio, reg, offset,
|
|
|
ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
|
|
|
if (mmio->is_write) {
|
|
|
+ /* Re-set level triggered level-active interrupts */
|
|
|
+ level_active = vgic_bitmap_get_reg(&dist->irq_level,
|
|
|
+ vcpu->vcpu_id, offset);
|
|
|
+ reg = vgic_bitmap_get_reg(&dist->irq_pending,
|
|
|
+ vcpu->vcpu_id, offset);
|
|
|
+ *reg |= *level_active;
|
|
|
+
|
|
|
+ /* Ignore writes to SGIs */
|
|
|
+ if (offset < 2) {
|
|
|
+ *reg &= ~0xffff;
|
|
|
+ *reg |= orig & 0xffff;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Clear soft-pending flags */
|
|
|
+ reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
|
|
|
+ vcpu->vcpu_id, offset);
|
|
|
+ vgic_reg_access(mmio, reg, offset,
|
|
|
+ ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
|
|
|
+
|
|
|
vgic_update_state(vcpu->kvm);
|
|
|
return true;
|
|
|
}
|
|
@@ -651,9 +788,9 @@ static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
|
|
|
* is fine, then we are only setting a few bits that were
|
|
|
* already set.
|
|
|
*/
|
|
|
- vgic_dist_irq_set(vcpu, lr.irq);
|
|
|
+ vgic_dist_irq_set_pending(vcpu, lr.irq);
|
|
|
if (lr.irq < VGIC_NR_SGIS)
|
|
|
- dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source;
|
|
|
+ *vgic_get_sgi_sources(dist, vcpu_id, lr.irq) |= 1 << lr.source;
|
|
|
lr.state &= ~LR_STATE_PENDING;
|
|
|
vgic_set_lr(vcpu, i, lr);
|
|
|
|
|
@@ -662,8 +799,10 @@ static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
|
|
|
* active), then the LR does not hold any useful info and can
|
|
|
* be marked as free for other use.
|
|
|
*/
|
|
|
- if (!(lr.state & LR_STATE_MASK))
|
|
|
+ if (!(lr.state & LR_STATE_MASK)) {
|
|
|
vgic_retire_lr(i, lr.irq, vcpu);
|
|
|
+ vgic_irq_clear_queued(vcpu, lr.irq);
|
|
|
+ }
|
|
|
|
|
|
/* Finally update the VGIC state. */
|
|
|
vgic_update_state(vcpu->kvm);
|
|
@@ -677,7 +816,7 @@ static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
|
|
|
{
|
|
|
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
|
|
int sgi;
|
|
|
- int min_sgi = (offset & ~0x3) * 4;
|
|
|
+ int min_sgi = (offset & ~0x3);
|
|
|
int max_sgi = min_sgi + 3;
|
|
|
int vcpu_id = vcpu->vcpu_id;
|
|
|
u32 reg = 0;
|
|
@@ -685,7 +824,7 @@ static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
|
|
|
/* Copy source SGIs from distributor side */
|
|
|
for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
|
|
|
int shift = 8 * (sgi - min_sgi);
|
|
|
- reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift;
|
|
|
+ reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift;
|
|
|
}
|
|
|
|
|
|
mmio_data_write(mmio, ~0, reg);
|
|
@@ -698,7 +837,7 @@ static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
|
|
|
{
|
|
|
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
|
|
int sgi;
|
|
|
- int min_sgi = (offset & ~0x3) * 4;
|
|
|
+ int min_sgi = (offset & ~0x3);
|
|
|
int max_sgi = min_sgi + 3;
|
|
|
int vcpu_id = vcpu->vcpu_id;
|
|
|
u32 reg;
|
|
@@ -709,14 +848,15 @@ static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
|
|
|
/* Clear pending SGIs on the distributor */
|
|
|
for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
|
|
|
u8 mask = reg >> (8 * (sgi - min_sgi));
|
|
|
+ u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi);
|
|
|
if (set) {
|
|
|
- if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask)
|
|
|
+ if ((*src & mask) != mask)
|
|
|
updated = true;
|
|
|
- dist->irq_sgi_sources[vcpu_id][sgi] |= mask;
|
|
|
+ *src |= mask;
|
|
|
} else {
|
|
|
- if (dist->irq_sgi_sources[vcpu_id][sgi] & mask)
|
|
|
+ if (*src & mask)
|
|
|
updated = true;
|
|
|
- dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask;
|
|
|
+ *src &= ~mask;
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -755,6 +895,7 @@ static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
|
|
|
struct mmio_range {
|
|
|
phys_addr_t base;
|
|
|
unsigned long len;
|
|
|
+ int bits_per_irq;
|
|
|
bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
|
|
|
phys_addr_t offset);
|
|
|
};
|
|
@@ -763,56 +904,67 @@ static const struct mmio_range vgic_dist_ranges[] = {
|
|
|
{
|
|
|
.base = GIC_DIST_CTRL,
|
|
|
.len = 12,
|
|
|
+ .bits_per_irq = 0,
|
|
|
.handle_mmio = handle_mmio_misc,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_IGROUP,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_raz_wi,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_ENABLE_SET,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_set_enable_reg,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_ENABLE_CLEAR,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_clear_enable_reg,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_PENDING_SET,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_set_pending_reg,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_PENDING_CLEAR,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_clear_pending_reg,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_ACTIVE_SET,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_raz_wi,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_ACTIVE_CLEAR,
|
|
|
- .len = VGIC_NR_IRQS / 8,
|
|
|
+ .len = VGIC_MAX_IRQS / 8,
|
|
|
+ .bits_per_irq = 1,
|
|
|
.handle_mmio = handle_mmio_raz_wi,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_PRI,
|
|
|
- .len = VGIC_NR_IRQS,
|
|
|
+ .len = VGIC_MAX_IRQS,
|
|
|
+ .bits_per_irq = 8,
|
|
|
.handle_mmio = handle_mmio_priority_reg,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_TARGET,
|
|
|
- .len = VGIC_NR_IRQS,
|
|
|
+ .len = VGIC_MAX_IRQS,
|
|
|
+ .bits_per_irq = 8,
|
|
|
.handle_mmio = handle_mmio_target_reg,
|
|
|
},
|
|
|
{
|
|
|
.base = GIC_DIST_CONFIG,
|
|
|
- .len = VGIC_NR_IRQS / 4,
|
|
|
+ .len = VGIC_MAX_IRQS / 4,
|
|
|
+ .bits_per_irq = 2,
|
|
|
.handle_mmio = handle_mmio_cfg_reg,
|
|
|
},
|
|
|
{
|
|
@@ -850,6 +1002,22 @@ struct mmio_range *find_matching_range(const struct mmio_range *ranges,
|
|
|
return NULL;
|
|
|
}
|
|
|
|
|
|
+static bool vgic_validate_access(const struct vgic_dist *dist,
|
|
|
+ const struct mmio_range *range,
|
|
|
+ unsigned long offset)
|
|
|
+{
|
|
|
+ int irq;
|
|
|
+
|
|
|
+ if (!range->bits_per_irq)
|
|
|
+ return true; /* Not an irq-based access */
|
|
|
+
|
|
|
+ irq = offset * 8 / range->bits_per_irq;
|
|
|
+ if (irq >= dist->nr_irqs)
|
|
|
+ return false;
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
/**
|
|
|
* vgic_handle_mmio - handle an in-kernel MMIO access
|
|
|
* @vcpu: pointer to the vcpu performing the access
|
|
@@ -889,7 +1057,13 @@ bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
|
|
|
|
|
spin_lock(&vcpu->kvm->arch.vgic.lock);
|
|
|
offset = mmio->phys_addr - range->base - base;
|
|
|
- updated_state = range->handle_mmio(vcpu, mmio, offset);
|
|
|
+ if (vgic_validate_access(dist, range, offset)) {
|
|
|
+ updated_state = range->handle_mmio(vcpu, mmio, offset);
|
|
|
+ } else {
|
|
|
+ vgic_reg_access(mmio, NULL, offset,
|
|
|
+ ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
|
|
|
+ updated_state = false;
|
|
|
+ }
|
|
|
spin_unlock(&vcpu->kvm->arch.vgic.lock);
|
|
|
kvm_prepare_mmio(run, mmio);
|
|
|
kvm_handle_mmio_return(vcpu, run);
|
|
@@ -900,6 +1074,11 @@ bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
|
|
return true;
|
|
|
}
|
|
|
|
|
|
+static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi)
|
|
|
+{
|
|
|
+ return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi;
|
|
|
+}
|
|
|
+
|
|
|
static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
|
|
|
{
|
|
|
struct kvm *kvm = vcpu->kvm;
|
|
@@ -932,8 +1111,8 @@ static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
|
|
|
kvm_for_each_vcpu(c, vcpu, kvm) {
|
|
|
if (target_cpus & 1) {
|
|
|
/* Flag the SGI as pending */
|
|
|
- vgic_dist_irq_set(vcpu, sgi);
|
|
|
- dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
|
|
|
+ vgic_dist_irq_set_pending(vcpu, sgi);
|
|
|
+ *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id;
|
|
|
kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
|
|
|
}
|
|
|
|
|
@@ -941,32 +1120,38 @@ static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+static int vgic_nr_shared_irqs(struct vgic_dist *dist)
|
|
|
+{
|
|
|
+ return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS;
|
|
|
+}
|
|
|
+
|
|
|
static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
|
|
|
{
|
|
|
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
|
|
unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
|
|
|
unsigned long pending_private, pending_shared;
|
|
|
+ int nr_shared = vgic_nr_shared_irqs(dist);
|
|
|
int vcpu_id;
|
|
|
|
|
|
vcpu_id = vcpu->vcpu_id;
|
|
|
pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
|
|
|
pend_shared = vcpu->arch.vgic_cpu.pending_shared;
|
|
|
|
|
|
- pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
|
|
|
+ pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id);
|
|
|
enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
|
|
|
bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
|
|
|
|
|
|
- pending = vgic_bitmap_get_shared_map(&dist->irq_state);
|
|
|
+ pending = vgic_bitmap_get_shared_map(&dist->irq_pending);
|
|
|
enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
|
|
|
- bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
|
|
|
+ bitmap_and(pend_shared, pending, enabled, nr_shared);
|
|
|
bitmap_and(pend_shared, pend_shared,
|
|
|
vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
|
|
|
- VGIC_NR_SHARED_IRQS);
|
|
|
+ nr_shared);
|
|
|
|
|
|
pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
|
|
|
- pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
|
|
|
+ pending_shared = find_first_bit(pend_shared, nr_shared);
|
|
|
return (pending_private < VGIC_NR_PRIVATE_IRQS ||
|
|
|
- pending_shared < VGIC_NR_SHARED_IRQS);
|
|
|
+ pending_shared < vgic_nr_shared_irqs(dist));
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -980,14 +1165,14 @@ static void vgic_update_state(struct kvm *kvm)
|
|
|
int c;
|
|
|
|
|
|
if (!dist->enabled) {
|
|
|
- set_bit(0, &dist->irq_pending_on_cpu);
|
|
|
+ set_bit(0, dist->irq_pending_on_cpu);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
kvm_for_each_vcpu(c, vcpu, kvm) {
|
|
|
if (compute_pending_for_cpu(vcpu)) {
|
|
|
pr_debug("CPU%d has pending interrupts\n", c);
|
|
|
- set_bit(c, &dist->irq_pending_on_cpu);
|
|
|
+ set_bit(c, dist->irq_pending_on_cpu);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
@@ -1079,8 +1264,8 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
|
|
|
|
|
|
if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
|
|
|
vgic_retire_lr(lr, vlr.irq, vcpu);
|
|
|
- if (vgic_irq_is_active(vcpu, vlr.irq))
|
|
|
- vgic_irq_clear_active(vcpu, vlr.irq);
|
|
|
+ if (vgic_irq_is_queued(vcpu, vlr.irq))
|
|
|
+ vgic_irq_clear_queued(vcpu, vlr.irq);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
@@ -1092,13 +1277,14 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
|
|
|
static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
|
|
|
{
|
|
|
struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
|
|
|
+ struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
|
|
struct vgic_lr vlr;
|
|
|
int lr;
|
|
|
|
|
|
/* Sanitize the input... */
|
|
|
BUG_ON(sgi_source_id & ~7);
|
|
|
BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
|
|
|
- BUG_ON(irq >= VGIC_NR_IRQS);
|
|
|
+ BUG_ON(irq >= dist->nr_irqs);
|
|
|
|
|
|
kvm_debug("Queue IRQ%d\n", irq);
|
|
|
|
|
@@ -1144,14 +1330,14 @@ static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
|
|
|
int vcpu_id = vcpu->vcpu_id;
|
|
|
int c;
|
|
|
|
|
|
- sources = dist->irq_sgi_sources[vcpu_id][irq];
|
|
|
+ sources = *vgic_get_sgi_sources(dist, vcpu_id, irq);
|
|
|
|
|
|
- for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
|
|
|
+ for_each_set_bit(c, &sources, dist->nr_cpus) {
|
|
|
if (vgic_queue_irq(vcpu, c, irq))
|
|
|
clear_bit(c, &sources);
|
|
|
}
|
|
|
|
|
|
- dist->irq_sgi_sources[vcpu_id][irq] = sources;
|
|
|
+ *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources;
|
|
|
|
|
|
/*
|
|
|
* If the sources bitmap has been cleared it means that we
|
|
@@ -1160,7 +1346,7 @@ static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
|
|
|
* our emulated gic and can get rid of them.
|
|
|
*/
|
|
|
if (!sources) {
|
|
|
- vgic_dist_irq_clear(vcpu, irq);
|
|
|
+ vgic_dist_irq_clear_pending(vcpu, irq);
|
|
|
vgic_cpu_irq_clear(vcpu, irq);
|
|
|
return true;
|
|
|
}
|
|
@@ -1170,15 +1356,15 @@ static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
|
|
|
|
|
|
static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
|
|
|
{
|
|
|
- if (vgic_irq_is_active(vcpu, irq))
|
|
|
+ if (!vgic_can_sample_irq(vcpu, irq))
|
|
|
return true; /* level interrupt, already queued */
|
|
|
|
|
|
if (vgic_queue_irq(vcpu, 0, irq)) {
|
|
|
if (vgic_irq_is_edge(vcpu, irq)) {
|
|
|
- vgic_dist_irq_clear(vcpu, irq);
|
|
|
+ vgic_dist_irq_clear_pending(vcpu, irq);
|
|
|
vgic_cpu_irq_clear(vcpu, irq);
|
|
|
} else {
|
|
|
- vgic_irq_set_active(vcpu, irq);
|
|
|
+ vgic_irq_set_queued(vcpu, irq);
|
|
|
}
|
|
|
|
|
|
return true;
|
|
@@ -1223,7 +1409,7 @@ static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
|
|
|
}
|
|
|
|
|
|
/* SPIs */
|
|
|
- for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
|
|
|
+ for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) {
|
|
|
if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
|
|
|
overflow = 1;
|
|
|
}
|
|
@@ -1239,7 +1425,7 @@ epilog:
|
|
|
* us. Claim we don't have anything pending. We'll
|
|
|
* adjust that if needed while exiting.
|
|
|
*/
|
|
|
- clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
|
|
|
+ clear_bit(vcpu_id, dist->irq_pending_on_cpu);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -1261,17 +1447,32 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
|
|
|
|
|
|
for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
|
|
|
struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
|
|
|
+ WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq));
|
|
|
|
|
|
- vgic_irq_clear_active(vcpu, vlr.irq);
|
|
|
+ vgic_irq_clear_queued(vcpu, vlr.irq);
|
|
|
WARN_ON(vlr.state & LR_STATE_MASK);
|
|
|
vlr.state = 0;
|
|
|
vgic_set_lr(vcpu, lr, vlr);
|
|
|
|
|
|
+ /*
|
|
|
+ * If the IRQ was EOIed it was also ACKed and we we
|
|
|
+ * therefore assume we can clear the soft pending
|
|
|
+ * state (should it had been set) for this interrupt.
|
|
|
+ *
|
|
|
+ * Note: if the IRQ soft pending state was set after
|
|
|
+ * the IRQ was acked, it actually shouldn't be
|
|
|
+ * cleared, but we have no way of knowing that unless
|
|
|
+ * we start trapping ACKs when the soft-pending state
|
|
|
+ * is set.
|
|
|
+ */
|
|
|
+ vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq);
|
|
|
+
|
|
|
/* Any additional pending interrupt? */
|
|
|
- if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) {
|
|
|
+ if (vgic_dist_irq_get_level(vcpu, vlr.irq)) {
|
|
|
vgic_cpu_irq_set(vcpu, vlr.irq);
|
|
|
level_pending = true;
|
|
|
} else {
|
|
|
+ vgic_dist_irq_clear_pending(vcpu, vlr.irq);
|
|
|
vgic_cpu_irq_clear(vcpu, vlr.irq);
|
|
|
}
|
|
|
|
|
@@ -1315,14 +1516,14 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
|
|
|
|
|
|
vlr = vgic_get_lr(vcpu, lr);
|
|
|
|
|
|
- BUG_ON(vlr.irq >= VGIC_NR_IRQS);
|
|
|
+ BUG_ON(vlr.irq >= dist->nr_irqs);
|
|
|
vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
|
|
|
}
|
|
|
|
|
|
/* Check if we still have something up our sleeve... */
|
|
|
pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
|
|
|
if (level_pending || pending < vgic->nr_lr)
|
|
|
- set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
|
|
|
+ set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
|
|
|
}
|
|
|
|
|
|
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
|
|
@@ -1356,7 +1557,7 @@ int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
|
|
|
if (!irqchip_in_kernel(vcpu->kvm))
|
|
|
return 0;
|
|
|
|
|
|
- return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
|
|
|
+ return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
|
|
|
}
|
|
|
|
|
|
static void vgic_kick_vcpus(struct kvm *kvm)
|
|
@@ -1376,34 +1577,36 @@ static void vgic_kick_vcpus(struct kvm *kvm)
|
|
|
|
|
|
static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
|
|
|
{
|
|
|
- int is_edge = vgic_irq_is_edge(vcpu, irq);
|
|
|
- int state = vgic_dist_irq_is_pending(vcpu, irq);
|
|
|
+ int edge_triggered = vgic_irq_is_edge(vcpu, irq);
|
|
|
|
|
|
/*
|
|
|
* Only inject an interrupt if:
|
|
|
* - edge triggered and we have a rising edge
|
|
|
* - level triggered and we change level
|
|
|
*/
|
|
|
- if (is_edge)
|
|
|
+ if (edge_triggered) {
|
|
|
+ int state = vgic_dist_irq_is_pending(vcpu, irq);
|
|
|
return level > state;
|
|
|
- else
|
|
|
+ } else {
|
|
|
+ int state = vgic_dist_irq_get_level(vcpu, irq);
|
|
|
return level != state;
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
-static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
|
|
|
+static bool vgic_update_irq_pending(struct kvm *kvm, int cpuid,
|
|
|
unsigned int irq_num, bool level)
|
|
|
{
|
|
|
struct vgic_dist *dist = &kvm->arch.vgic;
|
|
|
struct kvm_vcpu *vcpu;
|
|
|
- int is_edge, is_level;
|
|
|
+ int edge_triggered, level_triggered;
|
|
|
int enabled;
|
|
|
bool ret = true;
|
|
|
|
|
|
spin_lock(&dist->lock);
|
|
|
|
|
|
vcpu = kvm_get_vcpu(kvm, cpuid);
|
|
|
- is_edge = vgic_irq_is_edge(vcpu, irq_num);
|
|
|
- is_level = !is_edge;
|
|
|
+ edge_triggered = vgic_irq_is_edge(vcpu, irq_num);
|
|
|
+ level_triggered = !edge_triggered;
|
|
|
|
|
|
if (!vgic_validate_injection(vcpu, irq_num, level)) {
|
|
|
ret = false;
|
|
@@ -1417,10 +1620,19 @@ static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
|
|
|
|
|
|
kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
|
|
|
|
|
|
- if (level)
|
|
|
- vgic_dist_irq_set(vcpu, irq_num);
|
|
|
- else
|
|
|
- vgic_dist_irq_clear(vcpu, irq_num);
|
|
|
+ if (level) {
|
|
|
+ if (level_triggered)
|
|
|
+ vgic_dist_irq_set_level(vcpu, irq_num);
|
|
|
+ vgic_dist_irq_set_pending(vcpu, irq_num);
|
|
|
+ } else {
|
|
|
+ if (level_triggered) {
|
|
|
+ vgic_dist_irq_clear_level(vcpu, irq_num);
|
|
|
+ if (!vgic_dist_irq_soft_pend(vcpu, irq_num))
|
|
|
+ vgic_dist_irq_clear_pending(vcpu, irq_num);
|
|
|
+ } else {
|
|
|
+ vgic_dist_irq_clear_pending(vcpu, irq_num);
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
enabled = vgic_irq_is_enabled(vcpu, irq_num);
|
|
|
|
|
@@ -1429,7 +1641,7 @@ static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
|
|
|
goto out;
|
|
|
}
|
|
|
|
|
|
- if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
|
|
|
+ if (!vgic_can_sample_irq(vcpu, irq_num)) {
|
|
|
/*
|
|
|
* Level interrupt in progress, will be picked up
|
|
|
* when EOId.
|
|
@@ -1440,7 +1652,7 @@ static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
|
|
|
|
|
|
if (level) {
|
|
|
vgic_cpu_irq_set(vcpu, irq_num);
|
|
|
- set_bit(cpuid, &dist->irq_pending_on_cpu);
|
|
|
+ set_bit(cpuid, dist->irq_pending_on_cpu);
|
|
|
}
|
|
|
|
|
|
out:
|
|
@@ -1466,7 +1678,8 @@ out:
|
|
|
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
|
|
|
bool level)
|
|
|
{
|
|
|
- if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
|
|
|
+ if (likely(vgic_initialized(kvm)) &&
|
|
|
+ vgic_update_irq_pending(kvm, cpuid, irq_num, level))
|
|
|
vgic_kick_vcpus(kvm);
|
|
|
|
|
|
return 0;
|
|
@@ -1483,6 +1696,32 @@ static irqreturn_t vgic_maintenance_handler(int irq, void *data)
|
|
|
return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
+void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
|
|
|
+{
|
|
|
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
|
|
|
+
|
|
|
+ kfree(vgic_cpu->pending_shared);
|
|
|
+ kfree(vgic_cpu->vgic_irq_lr_map);
|
|
|
+ vgic_cpu->pending_shared = NULL;
|
|
|
+ vgic_cpu->vgic_irq_lr_map = NULL;
|
|
|
+}
|
|
|
+
|
|
|
+static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
|
|
|
+{
|
|
|
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
|
|
|
+
|
|
|
+ int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8;
|
|
|
+ vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL);
|
|
|
+ vgic_cpu->vgic_irq_lr_map = kzalloc(nr_irqs, GFP_KERNEL);
|
|
|
+
|
|
|
+ if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) {
|
|
|
+ kvm_vgic_vcpu_destroy(vcpu);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
/**
|
|
|
* kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
|
|
|
* @vcpu: pointer to the vcpu struct
|
|
@@ -1490,16 +1729,13 @@ static irqreturn_t vgic_maintenance_handler(int irq, void *data)
|
|
|
* Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
|
|
|
* this vcpu and enable the VGIC for this VCPU
|
|
|
*/
|
|
|
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
|
|
|
+static void kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
|
|
|
{
|
|
|
struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
|
|
|
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
|
|
int i;
|
|
|
|
|
|
- if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
|
|
|
- return -EBUSY;
|
|
|
-
|
|
|
- for (i = 0; i < VGIC_NR_IRQS; i++) {
|
|
|
+ for (i = 0; i < dist->nr_irqs; i++) {
|
|
|
if (i < VGIC_NR_PPIS)
|
|
|
vgic_bitmap_set_irq_val(&dist->irq_enabled,
|
|
|
vcpu->vcpu_id, i, 1);
|
|
@@ -1518,84 +1754,112 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
|
|
|
vgic_cpu->nr_lr = vgic->nr_lr;
|
|
|
|
|
|
vgic_enable(vcpu);
|
|
|
-
|
|
|
- return 0;
|
|
|
}
|
|
|
|
|
|
-static void vgic_init_maintenance_interrupt(void *info)
|
|
|
+void kvm_vgic_destroy(struct kvm *kvm)
|
|
|
{
|
|
|
- enable_percpu_irq(vgic->maint_irq, 0);
|
|
|
+ struct vgic_dist *dist = &kvm->arch.vgic;
|
|
|
+ struct kvm_vcpu *vcpu;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ kvm_for_each_vcpu(i, vcpu, kvm)
|
|
|
+ kvm_vgic_vcpu_destroy(vcpu);
|
|
|
+
|
|
|
+ vgic_free_bitmap(&dist->irq_enabled);
|
|
|
+ vgic_free_bitmap(&dist->irq_level);
|
|
|
+ vgic_free_bitmap(&dist->irq_pending);
|
|
|
+ vgic_free_bitmap(&dist->irq_soft_pend);
|
|
|
+ vgic_free_bitmap(&dist->irq_queued);
|
|
|
+ vgic_free_bitmap(&dist->irq_cfg);
|
|
|
+ vgic_free_bytemap(&dist->irq_priority);
|
|
|
+ if (dist->irq_spi_target) {
|
|
|
+ for (i = 0; i < dist->nr_cpus; i++)
|
|
|
+ vgic_free_bitmap(&dist->irq_spi_target[i]);
|
|
|
+ }
|
|
|
+ kfree(dist->irq_sgi_sources);
|
|
|
+ kfree(dist->irq_spi_cpu);
|
|
|
+ kfree(dist->irq_spi_target);
|
|
|
+ kfree(dist->irq_pending_on_cpu);
|
|
|
+ dist->irq_sgi_sources = NULL;
|
|
|
+ dist->irq_spi_cpu = NULL;
|
|
|
+ dist->irq_spi_target = NULL;
|
|
|
+ dist->irq_pending_on_cpu = NULL;
|
|
|
}
|
|
|
|
|
|
-static int vgic_cpu_notify(struct notifier_block *self,
|
|
|
- unsigned long action, void *cpu)
|
|
|
+/*
|
|
|
+ * Allocate and initialize the various data structures. Must be called
|
|
|
+ * with kvm->lock held!
|
|
|
+ */
|
|
|
+static int vgic_init_maps(struct kvm *kvm)
|
|
|
{
|
|
|
- switch (action) {
|
|
|
- case CPU_STARTING:
|
|
|
- case CPU_STARTING_FROZEN:
|
|
|
- vgic_init_maintenance_interrupt(NULL);
|
|
|
- break;
|
|
|
- case CPU_DYING:
|
|
|
- case CPU_DYING_FROZEN:
|
|
|
- disable_percpu_irq(vgic->maint_irq);
|
|
|
- break;
|
|
|
- }
|
|
|
+ struct vgic_dist *dist = &kvm->arch.vgic;
|
|
|
+ struct kvm_vcpu *vcpu;
|
|
|
+ int nr_cpus, nr_irqs;
|
|
|
+ int ret, i;
|
|
|
|
|
|
- return NOTIFY_OK;
|
|
|
-}
|
|
|
+ if (dist->nr_cpus) /* Already allocated */
|
|
|
+ return 0;
|
|
|
|
|
|
-static struct notifier_block vgic_cpu_nb = {
|
|
|
- .notifier_call = vgic_cpu_notify,
|
|
|
-};
|
|
|
+ nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus);
|
|
|
+ if (!nr_cpus) /* No vcpus? Can't be good... */
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
-static const struct of_device_id vgic_ids[] = {
|
|
|
- { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
|
|
|
- { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
|
|
|
- {},
|
|
|
-};
|
|
|
+ /*
|
|
|
+ * If nobody configured the number of interrupts, use the
|
|
|
+ * legacy one.
|
|
|
+ */
|
|
|
+ if (!dist->nr_irqs)
|
|
|
+ dist->nr_irqs = VGIC_NR_IRQS_LEGACY;
|
|
|
|
|
|
-int kvm_vgic_hyp_init(void)
|
|
|
-{
|
|
|
- const struct of_device_id *matched_id;
|
|
|
- int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
|
|
|
- const struct vgic_params **);
|
|
|
- struct device_node *vgic_node;
|
|
|
- int ret;
|
|
|
+ nr_irqs = dist->nr_irqs;
|
|
|
|
|
|
- vgic_node = of_find_matching_node_and_match(NULL,
|
|
|
- vgic_ids, &matched_id);
|
|
|
- if (!vgic_node) {
|
|
|
- kvm_err("error: no compatible GIC node found\n");
|
|
|
- return -ENODEV;
|
|
|
- }
|
|
|
+ ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs);
|
|
|
+ ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs);
|
|
|
+ ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs);
|
|
|
+ ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs);
|
|
|
+ ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs);
|
|
|
+ ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs);
|
|
|
+ ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs);
|
|
|
|
|
|
- vgic_probe = matched_id->data;
|
|
|
- ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
|
|
|
if (ret)
|
|
|
- return ret;
|
|
|
+ goto out;
|
|
|
|
|
|
- ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
|
|
|
- "vgic", kvm_get_running_vcpus());
|
|
|
- if (ret) {
|
|
|
- kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
|
|
|
- return ret;
|
|
|
+ dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL);
|
|
|
+ dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL);
|
|
|
+ dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus,
|
|
|
+ GFP_KERNEL);
|
|
|
+ dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!dist->irq_sgi_sources ||
|
|
|
+ !dist->irq_spi_cpu ||
|
|
|
+ !dist->irq_spi_target ||
|
|
|
+ !dist->irq_pending_on_cpu) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto out;
|
|
|
}
|
|
|
|
|
|
- ret = __register_cpu_notifier(&vgic_cpu_nb);
|
|
|
- if (ret) {
|
|
|
- kvm_err("Cannot register vgic CPU notifier\n");
|
|
|
- goto out_free_irq;
|
|
|
- }
|
|
|
+ for (i = 0; i < nr_cpus; i++)
|
|
|
+ ret |= vgic_init_bitmap(&dist->irq_spi_target[i],
|
|
|
+ nr_cpus, nr_irqs);
|
|
|
|
|
|
- /* Callback into for arch code for setup */
|
|
|
- vgic_arch_setup(vgic);
|
|
|
+ if (ret)
|
|
|
+ goto out;
|
|
|
|
|
|
- on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
|
|
|
+ kvm_for_each_vcpu(i, vcpu, kvm) {
|
|
|
+ ret = vgic_vcpu_init_maps(vcpu, nr_irqs);
|
|
|
+ if (ret) {
|
|
|
+ kvm_err("VGIC: Failed to allocate vcpu memory\n");
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
- return 0;
|
|
|
+ for (i = VGIC_NR_PRIVATE_IRQS; i < dist->nr_irqs; i += 4)
|
|
|
+ vgic_set_target_reg(kvm, 0, i);
|
|
|
+
|
|
|
+out:
|
|
|
+ if (ret)
|
|
|
+ kvm_vgic_destroy(kvm);
|
|
|
|
|
|
-out_free_irq:
|
|
|
- free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
@@ -1610,6 +1874,7 @@ out_free_irq:
|
|
|
*/
|
|
|
int kvm_vgic_init(struct kvm *kvm)
|
|
|
{
|
|
|
+ struct kvm_vcpu *vcpu;
|
|
|
int ret = 0, i;
|
|
|
|
|
|
if (!irqchip_in_kernel(kvm))
|
|
@@ -1627,6 +1892,12 @@ int kvm_vgic_init(struct kvm *kvm)
|
|
|
goto out;
|
|
|
}
|
|
|
|
|
|
+ ret = vgic_init_maps(kvm);
|
|
|
+ if (ret) {
|
|
|
+ kvm_err("Unable to allocate maps\n");
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
|
|
|
vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE);
|
|
|
if (ret) {
|
|
@@ -1634,11 +1905,13 @@ int kvm_vgic_init(struct kvm *kvm)
|
|
|
goto out;
|
|
|
}
|
|
|
|
|
|
- for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
|
|
|
- vgic_set_target_reg(kvm, 0, i);
|
|
|
+ kvm_for_each_vcpu(i, vcpu, kvm)
|
|
|
+ kvm_vgic_vcpu_init(vcpu);
|
|
|
|
|
|
kvm->arch.vgic.ready = true;
|
|
|
out:
|
|
|
+ if (ret)
|
|
|
+ kvm_vgic_destroy(kvm);
|
|
|
mutex_unlock(&kvm->lock);
|
|
|
return ret;
|
|
|
}
|
|
@@ -1690,7 +1963,7 @@ out:
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-static bool vgic_ioaddr_overlap(struct kvm *kvm)
|
|
|
+static int vgic_ioaddr_overlap(struct kvm *kvm)
|
|
|
{
|
|
|
phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
|
|
|
phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
|
|
@@ -1879,6 +2152,10 @@ static int vgic_attr_regs_access(struct kvm_device *dev,
|
|
|
|
|
|
mutex_lock(&dev->kvm->lock);
|
|
|
|
|
|
+ ret = vgic_init_maps(dev->kvm);
|
|
|
+ if (ret)
|
|
|
+ goto out;
|
|
|
+
|
|
|
if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
|
|
|
ret = -EINVAL;
|
|
|
goto out;
|
|
@@ -1976,6 +2253,36 @@ static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|
|
|
|
|
return vgic_attr_regs_access(dev, attr, ®, true);
|
|
|
}
|
|
|
+ case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
|
|
|
+ u32 __user *uaddr = (u32 __user *)(long)attr->addr;
|
|
|
+ u32 val;
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ if (get_user(val, uaddr))
|
|
|
+ return -EFAULT;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * We require:
|
|
|
+ * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
|
|
|
+ * - at most 1024 interrupts
|
|
|
+ * - a multiple of 32 interrupts
|
|
|
+ */
|
|
|
+ if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
|
|
|
+ val > VGIC_MAX_IRQS ||
|
|
|
+ (val & 31))
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ mutex_lock(&dev->kvm->lock);
|
|
|
+
|
|
|
+ if (vgic_initialized(dev->kvm) || dev->kvm->arch.vgic.nr_irqs)
|
|
|
+ ret = -EBUSY;
|
|
|
+ else
|
|
|
+ dev->kvm->arch.vgic.nr_irqs = val;
|
|
|
+
|
|
|
+ mutex_unlock(&dev->kvm->lock);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
|
|
|
}
|
|
|
|
|
@@ -2012,6 +2319,11 @@ static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|
|
r = put_user(reg, uaddr);
|
|
|
break;
|
|
|
}
|
|
|
+ case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
|
|
|
+ u32 __user *uaddr = (u32 __user *)(long)attr->addr;
|
|
|
+ r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr);
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
}
|
|
|
|
|
@@ -2048,6 +2360,8 @@ static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|
|
case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
|
|
|
offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
|
|
|
return vgic_has_attr_regs(vgic_cpu_ranges, offset);
|
|
|
+ case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
|
|
|
+ return 0;
|
|
|
}
|
|
|
return -ENXIO;
|
|
|
}
|
|
@@ -2062,7 +2376,7 @@ static int vgic_create(struct kvm_device *dev, u32 type)
|
|
|
return kvm_vgic_create(dev->kvm);
|
|
|
}
|
|
|
|
|
|
-struct kvm_device_ops kvm_arm_vgic_v2_ops = {
|
|
|
+static struct kvm_device_ops kvm_arm_vgic_v2_ops = {
|
|
|
.name = "kvm-arm-vgic",
|
|
|
.create = vgic_create,
|
|
|
.destroy = vgic_destroy,
|
|
@@ -2070,3 +2384,81 @@ struct kvm_device_ops kvm_arm_vgic_v2_ops = {
|
|
|
.get_attr = vgic_get_attr,
|
|
|
.has_attr = vgic_has_attr,
|
|
|
};
|
|
|
+
|
|
|
+static void vgic_init_maintenance_interrupt(void *info)
|
|
|
+{
|
|
|
+ enable_percpu_irq(vgic->maint_irq, 0);
|
|
|
+}
|
|
|
+
|
|
|
+static int vgic_cpu_notify(struct notifier_block *self,
|
|
|
+ unsigned long action, void *cpu)
|
|
|
+{
|
|
|
+ switch (action) {
|
|
|
+ case CPU_STARTING:
|
|
|
+ case CPU_STARTING_FROZEN:
|
|
|
+ vgic_init_maintenance_interrupt(NULL);
|
|
|
+ break;
|
|
|
+ case CPU_DYING:
|
|
|
+ case CPU_DYING_FROZEN:
|
|
|
+ disable_percpu_irq(vgic->maint_irq);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ return NOTIFY_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static struct notifier_block vgic_cpu_nb = {
|
|
|
+ .notifier_call = vgic_cpu_notify,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct of_device_id vgic_ids[] = {
|
|
|
+ { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
|
|
|
+ { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+int kvm_vgic_hyp_init(void)
|
|
|
+{
|
|
|
+ const struct of_device_id *matched_id;
|
|
|
+ const int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
|
|
|
+ const struct vgic_params **);
|
|
|
+ struct device_node *vgic_node;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ vgic_node = of_find_matching_node_and_match(NULL,
|
|
|
+ vgic_ids, &matched_id);
|
|
|
+ if (!vgic_node) {
|
|
|
+ kvm_err("error: no compatible GIC node found\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ vgic_probe = matched_id->data;
|
|
|
+ ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
|
|
|
+ "vgic", kvm_get_running_vcpus());
|
|
|
+ if (ret) {
|
|
|
+ kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = __register_cpu_notifier(&vgic_cpu_nb);
|
|
|
+ if (ret) {
|
|
|
+ kvm_err("Cannot register vgic CPU notifier\n");
|
|
|
+ goto out_free_irq;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Callback into for arch code for setup */
|
|
|
+ vgic_arch_setup(vgic);
|
|
|
+
|
|
|
+ on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
|
|
|
+
|
|
|
+ return kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
|
|
|
+ KVM_DEV_TYPE_ARM_VGIC_V2);
|
|
|
+
|
|
|
+out_free_irq:
|
|
|
+ free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
|
|
|
+ return ret;
|
|
|
+}
|