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@@ -311,33 +311,42 @@ err_free:
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return ret;
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}
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-static void __init sun5i_timer_init(struct device_node *node)
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+static int __init sun5i_timer_init(struct device_node *node)
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{
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struct reset_control *rstc;
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void __iomem *timer_base;
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struct clk *clk;
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- int irq;
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+ int irq, ret;
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timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
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- if (IS_ERR(timer_base))
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- panic("Can't map registers");
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+ if (IS_ERR(timer_base)) {
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+ pr_err("Can't map registers");
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+ return PTR_ERR(timer_base);;
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+ }
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irq = irq_of_parse_and_map(node, 0);
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- if (irq <= 0)
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- panic("Can't parse IRQ");
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+ if (irq <= 0) {
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+ pr_err("Can't parse IRQ");
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+ return -EINVAL;
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+ }
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clk = of_clk_get(node, 0);
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- if (IS_ERR(clk))
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- panic("Can't get timer clock");
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+ if (IS_ERR(clk)) {
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+ pr_err("Can't get timer clock");
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+ return PTR_ERR(clk);
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+ }
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rstc = of_reset_control_get(node, NULL);
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if (!IS_ERR(rstc))
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reset_control_deassert(rstc);
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- sun5i_setup_clocksource(node, timer_base, clk, irq);
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- sun5i_setup_clockevent(node, timer_base, clk, irq);
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+ ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
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+ if (ret)
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+ return ret;
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+
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+ return sun5i_setup_clockevent(node, timer_base, clk, irq);
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}
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-CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
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- sun5i_timer_init);
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-CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
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- sun5i_timer_init);
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+CLOCKSOURCE_OF_DECLARE_RET(sun5i_a13, "allwinner,sun5i-a13-hstimer",
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+ sun5i_timer_init);
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+CLOCKSOURCE_OF_DECLARE_RET(sun7i_a20, "allwinner,sun7i-a20-hstimer",
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+ sun5i_timer_init);
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