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+/*
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+ * Copied from the kernel sources:
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+ *
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+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
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+ */
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+#ifndef _TOOLS_LINUX_ASM_POWERPC_BARRIER_H
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+#define _TOOLS_LINUX_ASM_POWERPC_BARRIER_H
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+
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+/*
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+ * Memory barrier.
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+ * The sync instruction guarantees that all memory accesses initiated
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+ * by this processor have been performed (with respect to all other
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+ * mechanisms that access memory). The eieio instruction is a barrier
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+ * providing an ordering (separately) for (a) cacheable stores and (b)
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+ * loads and stores to non-cacheable memory (e.g. I/O devices).
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+ *
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+ * mb() prevents loads and stores being reordered across this point.
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+ * rmb() prevents loads being reordered across this point.
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+ * wmb() prevents stores being reordered across this point.
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+ *
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+ * *mb() variants without smp_ prefix must order all types of memory
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+ * operations with one another. sync is the only instruction sufficient
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+ * to do this.
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+ */
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+#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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+#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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+#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
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+
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+#endif /* _TOOLS_LINUX_ASM_POWERPC_BARRIER_H */
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