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@@ -10,7 +10,8 @@
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#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
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#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
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-#define SUN8I_HDMI_PHY_DBG_CTRL_POL(val) (val << 8)
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+#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8)
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+#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)
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@@ -35,14 +36,14 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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u32 val = 0;
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- if ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
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- (mode->flags & DRM_MODE_FLAG_NHSYNC)) {
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- val = 0x03;
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- }
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+ if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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+ val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
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+
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+ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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+ val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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- SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK,
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- SUN8I_HDMI_PHY_DBG_CTRL_POL(val));
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+ SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
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