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drm/i915/bxt: add workaround to avoid PTE corruption

Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing
corrupted pte entries.

v2:
- move the workaround to bxt_init_clock_gating (imre)

Signed-off-by: Robert Beckett <robert.beckett@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Robert Beckett 10 years ago
parent
8d09c8123d
commit
e3a290553f
2 changed files with 3 additions and 0 deletions
Unified View Show Diff Stats
  1. 1 0
      drivers/gpu/drm/i915/i915_reg.h
  2. 2 0
      drivers/gpu/drm/i915/intel_pm.c

+ 1 - 0
drivers/gpu/drm/i915/i915_reg.h
View File 

@@ -1150,6 +1150,7 @@ enum skl_disp_power_wells {
 
 /* control register for cpu gtt access */
 
 /* control register for cpu gtt access */
 
 #define TILECTL				0x101000
 
 #define TILECTL				0x101000
 
 #define   TILECTL_SWZCTL			(1 << 0)
 
 #define   TILECTL_SWZCTL			(1 << 0)
 
+#define   TILECTL_TLBPF			(1 << 1)
 
 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
 
 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
 
 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
 
 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)

+ 2 - 0
drivers/gpu/drm/i915/intel_pm.c
View File 

@@ -110,6 +110,8 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 
 		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
 		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
 
 
+	/* FIXME: apply on A0 only */
 
+	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
 }
 
 }
 
 
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)