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@@ -1113,6 +1113,11 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
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amdgpu_dpm_enable_uvd(adev, false);
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} else {
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amdgpu_asic_set_uvd_clocks(adev, 0, 0);
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+ /* shutdown the UVD block */
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+ amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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+ AMD_PG_STATE_GATE);
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+ amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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+ AMD_CG_STATE_GATE);
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}
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} else {
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schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
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@@ -1129,6 +1134,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
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amdgpu_dpm_enable_uvd(adev, true);
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} else {
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amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
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+ amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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+ AMD_CG_STATE_UNGATE);
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+ amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
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+ AMD_PG_STATE_UNGATE);
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}
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}
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}
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