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@@ -4556,14 +4556,19 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
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* 400MHz
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* So we check to see whether we're above 90% of the lower bin and
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* adjust if needed.
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+ *
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+ * We seem to get an unstable or solid color picture at 200MHz.
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+ * Not sure what's wrong. For now use 200MHz only when all pipes
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+ * are off.
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*/
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if (max_pixclk > freq_320*9/10)
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return 400000;
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else if (max_pixclk > 266667*9/10)
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return freq_320;
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- else
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+ else if (max_pixclk > 0)
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return 266667;
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- /* Looks like the 200MHz CDclk freq doesn't work on some configs */
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+ else
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+ return 200000;
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}
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/* compute the max pixel clock for new configuration */
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