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@@ -7,7 +7,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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-#include <linux/sh_clk.h>
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+#include <linux/clk-provider.h>
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#include "rsnd.h"
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#define CLKA 0
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@@ -16,12 +16,26 @@
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#define CLKI 3
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#define CLKMAX 4
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+#define CLKOUT 0
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+#define CLKOUT1 1
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+#define CLKOUT2 2
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+#define CLKOUT3 3
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+#define CLKOUTMAX 4
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+
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+#define BRRx_MASK(x) (0x3FF & x)
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+
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+static struct rsnd_mod_ops adg_ops = {
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+ .name = "adg",
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+};
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+
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struct rsnd_adg {
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struct clk *clk[CLKMAX];
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+ struct clk *clkout[CLKOUTMAX];
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+ struct clk_onecell_data onecell;
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+ struct rsnd_mod mod;
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- int rbga_rate_for_441khz_div_6; /* RBGA */
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- int rbgb_rate_for_48khz_div_6; /* RBGB */
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- u32 ckr;
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+ int rbga_rate_for_441khz; /* RBGA */
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+ int rbgb_rate_for_48khz; /* RBGB */
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};
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#define for_each_rsnd_clk(pos, adg, i) \
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@@ -29,8 +43,28 @@ struct rsnd_adg {
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(i < CLKMAX) && \
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((pos) = adg->clk[i]); \
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i++)
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+#define for_each_rsnd_clkout(pos, adg, i) \
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+ for (i = 0; \
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+ (i < CLKOUTMAX) && \
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+ ((pos) = adg->clkout[i]); \
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+ i++)
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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+static u32 rsnd_adg_calculate_rbgx(unsigned long div)
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+{
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+ int i, ratio;
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+
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+ if (!div)
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+ return 0;
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+
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+ for (i = 3; i >= 0; i--) {
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+ ratio = 2 << (i * 2);
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+ if (0 == (div % ratio))
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+ return (u32)((i << 8) | ((div / ratio) - 1));
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+ }
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+
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+ return ~0;
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+}
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static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
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{
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@@ -60,6 +94,9 @@ static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
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int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
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struct rsnd_dai_stream *io)
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{
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+ struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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+ struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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int id = rsnd_mod_id(mod);
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int shift = (id % 2) ? 16 : 0;
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u32 mask, val;
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@@ -69,21 +106,26 @@ int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
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val = val << shift;
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mask = 0xffff << shift;
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- rsnd_mod_bset(mod, CMDOUT_TIMSEL, mask, val);
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+ rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
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return 0;
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}
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-static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *mod,
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+static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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u32 timsel)
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{
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+ struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
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+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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+ struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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int is_play = rsnd_io_is_play(io);
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- int id = rsnd_mod_id(mod);
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+ int id = rsnd_mod_id(src_mod);
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int shift = (id % 2) ? 16 : 0;
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u32 mask, ws;
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u32 in, out;
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+ rsnd_mod_confirm_src(src_mod);
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+
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ws = rsnd_adg_ssi_ws_timing_gen2(io);
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in = (is_play) ? timsel : ws;
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@@ -95,37 +137,38 @@ static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *mod,
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switch (id / 2) {
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case 0:
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- rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in);
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- rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
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+ rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
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+ rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
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break;
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case 1:
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- rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in);
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- rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
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+ rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
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+ rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
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break;
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case 2:
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- rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in);
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- rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
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+ rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
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+ rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
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break;
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case 3:
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- rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in);
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- rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
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+ rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
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+ rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
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break;
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case 4:
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- rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in);
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- rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
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+ rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
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+ rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
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break;
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}
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return 0;
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}
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-int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
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+int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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unsigned int src_rate,
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unsigned int dst_rate)
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{
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- struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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+ struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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+ struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, step, ret;
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u32 val, en;
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@@ -134,10 +177,12 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
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clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
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clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
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- adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
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- adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
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+ adg->rbga_rate_for_441khz, /* 0011: RBGA */
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+ adg->rbgb_rate_for_48khz, /* 0100: RBGB */
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};
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+ rsnd_mod_confirm_src(src_mod);
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+
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min = ~0;
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val = 0;
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en = 0;
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@@ -175,25 +220,27 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
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return -EIO;
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}
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- ret = rsnd_adg_set_src_timsel_gen2(mod, io, val);
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+ ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
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if (ret < 0) {
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dev_err(dev, "timsel error\n");
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return ret;
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}
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- rsnd_mod_bset(mod, DIV_EN, en, en);
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+ rsnd_mod_bset(adg_mod, DIV_EN, en, en);
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dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
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return 0;
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}
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-int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
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+int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io)
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{
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u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
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- return rsnd_adg_set_src_timsel_gen2(mod, io, val);
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+ rsnd_mod_confirm_src(src_mod);
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+
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+ return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
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}
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int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
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@@ -202,6 +249,7 @@ int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
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unsigned int dst_rate)
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{
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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+ struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, shift;
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u32 mask, val;
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@@ -211,8 +259,8 @@ int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
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clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
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0, /* 011: MLBCLK (not used) */
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- adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
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- adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
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+ adg->rbga_rate_for_441khz, /* 100: RBGA */
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+ adg->rbgb_rate_for_48khz, /* 101: RBGB */
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};
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/* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
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@@ -238,13 +286,13 @@ find_rate:
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switch (id / 4) {
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case 0:
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- rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
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+ rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL3, mask, val);
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break;
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case 1:
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- rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
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+ rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL4, mask, val);
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break;
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case 2:
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- rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
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+ rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL5, mask, val);
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break;
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}
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@@ -257,12 +305,17 @@ find_rate:
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return 0;
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}
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-static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
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+static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
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{
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- int id = rsnd_mod_id(mod);
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+ struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
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+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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+ struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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+ int id = rsnd_mod_id(ssi_mod);
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int shift = (id % 4) * 8;
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u32 mask = 0xFF << shift;
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+ rsnd_mod_confirm_ssi(ssi_mod);
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+
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val = val << shift;
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/*
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@@ -274,13 +327,13 @@ static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
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switch (id / 4) {
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case 0:
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- rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
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+ rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
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break;
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case 1:
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- rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
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+ rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
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break;
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case 2:
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- rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
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+ rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
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break;
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}
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}
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@@ -326,14 +379,14 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
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}
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/*
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- * find 1/6 clock from BRGA/BRGB
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+ * find divided clock from BRGA/BRGB
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*/
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- if (rate == adg->rbga_rate_for_441khz_div_6) {
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+ if (rate == adg->rbga_rate_for_441khz) {
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data = 0x10;
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goto found_clock;
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}
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- if (rate == adg->rbgb_rate_for_48khz_div_6) {
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+ if (rate == adg->rbgb_rate_for_48khz) {
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data = 0x20;
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goto found_clock;
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}
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@@ -342,29 +395,60 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
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found_clock:
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- /* see rsnd_adg_ssi_clk_init() */
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- rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
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- rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
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- rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
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-
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/*
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* This "mod" = "ssi" here.
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* we can get "ssi id" from mod
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*/
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rsnd_adg_set_ssi_clk(mod, data);
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- dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
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- rsnd_mod_id(mod), i, rate);
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+ dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
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+ rsnd_mod_name(mod), rsnd_mod_id(mod),
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+ data, rate);
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return 0;
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}
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-static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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+static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
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+ struct rsnd_adg *adg)
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{
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+ struct device *dev = rsnd_priv_to_dev(priv);
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struct clk *clk;
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- unsigned long rate;
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- u32 ckr;
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+ static const char * const clk_name[] = {
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+ [CLKA] = "clk_a",
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+ [CLKB] = "clk_b",
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+ [CLKC] = "clk_c",
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+ [CLKI] = "clk_i",
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+ };
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int i;
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+
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+ for (i = 0; i < CLKMAX; i++) {
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+ clk = devm_clk_get(dev, clk_name[i]);
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+ adg->clk[i] = IS_ERR(clk) ? NULL : clk;
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+ }
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+
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+ for_each_rsnd_clk(clk, adg, i)
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+ dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
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+}
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+
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+static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
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+ struct rsnd_adg *adg)
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+{
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+ struct clk *clk;
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+ struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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+ struct device *dev = rsnd_priv_to_dev(priv);
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+ struct device_node *np = dev->of_node;
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+ u32 ckr, rbgx, rbga, rbgb;
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+ u32 rate, req_rate, div;
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+ uint32_t count = 0;
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+ unsigned long req_48kHz_rate, req_441kHz_rate;
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+ int i;
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+ const char *parent_clk_name = NULL;
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+ static const char * const clkout_name[] = {
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+ [CLKOUT] = "audio_clkout",
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+ [CLKOUT1] = "audio_clkout1",
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+ [CLKOUT2] = "audio_clkout2",
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+ [CLKOUT3] = "audio_clkout3",
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+ };
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int brg_table[] = {
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[CLKA] = 0x0,
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[CLKB] = 0x1,
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@@ -372,19 +456,34 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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[CLKI] = 0x2,
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};
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+ of_property_read_u32(np, "#clock-cells", &count);
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+
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+ /*
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+ * ADG supports BRRA/BRRB output only
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+ * this means all clkout0/1/2/3 will be same rate
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+ */
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+ of_property_read_u32(np, "clock-frequency", &req_rate);
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+ req_48kHz_rate = 0;
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+ req_441kHz_rate = 0;
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+ if (0 == (req_rate % 44100))
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+ req_441kHz_rate = req_rate;
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+ if (0 == (req_rate % 48000))
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+ req_48kHz_rate = req_rate;
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+
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/*
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* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
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* have 44.1kHz or 48kHz base clocks for now.
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*
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* SSI itself can divide parent clock by 1/1 - 1/16
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- * So, BRGA outputs 44.1kHz base parent clock 1/32,
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- * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
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* see
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* rsnd_adg_ssi_clk_try_start()
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+ * rsnd_ssi_master_clk_start()
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*/
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ckr = 0;
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- adg->rbga_rate_for_441khz_div_6 = 0;
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- adg->rbgb_rate_for_48khz_div_6 = 0;
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+ rbga = 2; /* default 1/6 */
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+ rbgb = 2; /* default 1/6 */
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+ adg->rbga_rate_for_441khz = 0;
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+ adg->rbgb_rate_for_48khz = 0;
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for_each_rsnd_clk(clk, adg, i) {
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rate = clk_get_rate(clk);
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@@ -392,19 +491,86 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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continue;
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/* RBGA */
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- if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
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- adg->rbga_rate_for_441khz_div_6 = rate / 6;
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- ckr |= brg_table[i] << 20;
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+ if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
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+ div = 6;
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+ if (req_441kHz_rate)
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+ div = rate / req_441kHz_rate;
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+ rbgx = rsnd_adg_calculate_rbgx(div);
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+ if (BRRx_MASK(rbgx) == rbgx) {
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+ rbga = rbgx;
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+ adg->rbga_rate_for_441khz = rate / div;
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+ ckr |= brg_table[i] << 20;
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+ if (req_441kHz_rate)
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+ parent_clk_name = __clk_get_name(clk);
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+ }
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}
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/* RBGB */
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- if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
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- adg->rbgb_rate_for_48khz_div_6 = rate / 6;
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- ckr |= brg_table[i] << 16;
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+ if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
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+ div = 6;
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+ if (req_48kHz_rate)
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+ div = rate / req_48kHz_rate;
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+ rbgx = rsnd_adg_calculate_rbgx(div);
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+ if (BRRx_MASK(rbgx) == rbgx) {
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+ rbgb = rbgx;
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+ adg->rbgb_rate_for_48khz = rate / div;
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+ ckr |= brg_table[i] << 16;
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+ if (req_48kHz_rate) {
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+ parent_clk_name = __clk_get_name(clk);
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+ ckr |= 0x80000000;
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+ }
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+ }
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+ }
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+ }
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+
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+ /*
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+ * ADG supports BRRA/BRRB output only.
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+ * this means all clkout0/1/2/3 will be * same rate
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+ */
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+
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+ /*
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+ * for clkout
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+ */
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+ if (!count) {
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+ clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
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+ parent_clk_name,
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+ (parent_clk_name) ?
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+ 0 : CLK_IS_ROOT, req_rate);
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+ if (!IS_ERR(clk)) {
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+ adg->clkout[CLKOUT] = clk;
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+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
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+ }
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+ }
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+ /*
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+ * for clkout0/1/2/3
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+ */
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+ else {
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+ for (i = 0; i < CLKOUTMAX; i++) {
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+ clk = clk_register_fixed_rate(dev, clkout_name[i],
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+ parent_clk_name,
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+ (parent_clk_name) ?
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+ 0 : CLK_IS_ROOT,
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+ req_rate);
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+ if (!IS_ERR(clk)) {
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+ adg->onecell.clks = adg->clkout;
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+ adg->onecell.clk_num = CLKOUTMAX;
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+
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+ adg->clkout[i] = clk;
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+
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+ of_clk_add_provider(np, of_clk_src_onecell_get,
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+ &adg->onecell);
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+ }
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}
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}
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- adg->ckr = ckr;
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+ rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);
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+ rsnd_mod_write(adg_mod, BRRA, rbga);
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+ rsnd_mod_write(adg_mod, BRRB, rbgb);
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+
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+ for_each_rsnd_clkout(clk, adg, i)
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+ dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
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+ dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
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+ ckr, rbga, rbgb);
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}
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|
int rsnd_adg_probe(struct platform_device *pdev,
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|
@@ -413,8 +579,6 @@ int rsnd_adg_probe(struct platform_device *pdev,
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{
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struct rsnd_adg *adg;
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struct device *dev = rsnd_priv_to_dev(priv);
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- struct clk *clk;
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- int i;
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adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
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if (!adg) {
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|
@@ -422,15 +586,16 @@ int rsnd_adg_probe(struct platform_device *pdev,
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return -ENOMEM;
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}
|
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- adg->clk[CLKA] = devm_clk_get(dev, "clk_a");
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- adg->clk[CLKB] = devm_clk_get(dev, "clk_b");
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- adg->clk[CLKC] = devm_clk_get(dev, "clk_c");
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- adg->clk[CLKI] = devm_clk_get(dev, "clk_i");
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-
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- for_each_rsnd_clk(clk, adg, i)
|
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- dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
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|
+ /*
|
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|
+ * ADG is special module.
|
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|
+ * Use ADG mod without rsnd_mod_init() to make debug easy
|
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|
+ * for rsnd_write/rsnd_read
|
|
|
+ */
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|
+ adg->mod.ops = &adg_ops;
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|
+ adg->mod.priv = priv;
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|
|
- rsnd_adg_ssi_clk_init(priv, adg);
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|
+ rsnd_adg_get_clkin(priv, adg);
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|
+ rsnd_adg_get_clkout(priv, adg);
|
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|
|
priv->adg = adg;
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Mark Brown
10 years ago