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@@ -96,6 +96,9 @@
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/* GPIO upper 16 bit mask */
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#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
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+/* For GPIO quirks */
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+#define ZYNQ_GPIO_QUIRK_FOO BIT(0)
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+
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/**
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* struct zynq_gpio - gpio device private data structure
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* @chip: instance of the gpio_chip
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@@ -122,6 +125,7 @@ struct zynq_gpio {
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*/
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struct zynq_platform_data {
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const char *label;
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+ u32 quirks;
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u16 ngpio;
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int max_bank;
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int bank_min[ZYNQMP_GPIO_MAX_BANK];
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@@ -238,13 +242,19 @@ static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
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static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
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{
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u32 reg;
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+ bool is_zynq_gpio;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio *gpio = gpiochip_get_data(chip);
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+ is_zynq_gpio = gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_FOO;
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
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- /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
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- if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
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+ /*
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+ * On zynq bank 0 pins 7 and 8 are special and cannot be used
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+ * as inputs.
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+ */
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+ if (is_zynq_gpio && bank_num == 0 &&
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+ (bank_pin_num == 7 || bank_pin_num == 8))
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return -EINVAL;
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/* clear the bit in direction mode reg to set the pin as input */
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@@ -627,6 +637,7 @@ static const struct zynq_platform_data zynqmp_gpio_def = {
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static const struct zynq_platform_data zynq_gpio_def = {
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.label = "zynq_gpio",
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+ .quirks = ZYNQ_GPIO_QUIRK_FOO,
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.ngpio = ZYNQ_GPIO_NR_GPIOS,
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.max_bank = ZYNQ_GPIO_MAX_BANK,
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.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
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