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@@ -100,6 +100,15 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
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dma_release_channel(dws->rxchan);
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}
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+static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
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+ if (dma_width == 1)
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+ return DMA_SLAVE_BUSWIDTH_1_BYTE;
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+ else if (dma_width == 2)
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+ return DMA_SLAVE_BUSWIDTH_2_BYTES;
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+
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+ return DMA_SLAVE_BUSWIDTH_UNDEFINED;
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+}
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+
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
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* channel will clear a corresponding bit.
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@@ -126,7 +135,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = LNW_DMA_MSIZE_16;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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- txconf.dst_addr_width = dws->dma_width;
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+ txconf.dst_addr_width = convert_dma_width(dws->dma_width);
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txconf.device_fc = false;
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dmaengine_slave_config(dws->txchan, &txconf);
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@@ -175,7 +184,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = LNW_DMA_MSIZE_16;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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- rxconf.src_addr_width = dws->dma_width;
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+ rxconf.src_addr_width = convert_dma_width(dws->dma_width);
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rxconf.device_fc = false;
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dmaengine_slave_config(dws->rxchan, &rxconf);
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