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@@ -1014,6 +1014,7 @@ static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
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{
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struct brcmf_chip *pub;
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struct brcmf_core_priv *cc;
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+ struct brcmf_core *pmu;
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u32 base;
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u32 val;
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int ret = 0;
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@@ -1030,9 +1031,10 @@ static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
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capabilities_ext));
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/* get pmu caps & rev */
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+ pmu = brcmf_chip_get_pmu(pub); /* after reading cc_caps_ext */
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if (pub->cc_caps & CC_CAP_PMU) {
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val = chip->ops->read32(chip->ctx,
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- CORE_CC_REG(base, pmucapabilities));
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+ CORE_CC_REG(pmu->base, pmucapabilities));
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pub->pmurev = val & PCAP_REV_MASK;
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pub->pmucaps = val;
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}
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@@ -1131,6 +1133,23 @@ struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
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return &cc->pub;
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}
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+struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
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+{
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+ struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
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+ struct brcmf_core *pmu;
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+
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+ /* See if there is separated PMU core available */
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+ if (cc->rev >= 35 &&
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+ pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
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+ pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
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+ if (pmu)
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+ return pmu;
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+ }
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+
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+ /* Fallback to ChipCommon core for older hardware */
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+ return cc;
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+}
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+
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bool brcmf_chip_iscoreup(struct brcmf_core *pub)
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{
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struct brcmf_core_priv *core;
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@@ -1301,6 +1320,7 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
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{
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u32 base, addr, reg, pmu_cc3_mask = ~0;
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struct brcmf_chip_priv *chip;
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+ struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
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brcmf_dbg(TRACE, "Enter\n");
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@@ -1320,9 +1340,9 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
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case BRCM_CC_4335_CHIP_ID:
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case BRCM_CC_4339_CHIP_ID:
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/* read PMU chipcontrol register 3 */
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- addr = CORE_CC_REG(base, chipcontrol_addr);
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+ addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
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chip->ops->write32(chip->ctx, addr, 3);
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- addr = CORE_CC_REG(base, chipcontrol_data);
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+ addr = CORE_CC_REG(pmu->base, chipcontrol_data);
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reg = chip->ops->read32(chip->ctx, addr);
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return (reg & pmu_cc3_mask) != 0;
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case BRCM_CC_43430_CHIP_ID:
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@@ -1330,12 +1350,12 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
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reg = chip->ops->read32(chip->ctx, addr);
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return reg != 0;
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default:
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- addr = CORE_CC_REG(base, pmucapabilities_ext);
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+ addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
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reg = chip->ops->read32(chip->ctx, addr);
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if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
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return false;
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- addr = CORE_CC_REG(base, retention_ctl);
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+ addr = CORE_CC_REG(pmu->base, retention_ctl);
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reg = chip->ops->read32(chip->ctx, addr);
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return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
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PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
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