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@@ -552,6 +552,25 @@ static int mmhub_v1_0_set_clockgating_state(void *handle,
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return 0;
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return 0;
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}
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}
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+static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags)
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+{
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+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+ int data;
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+
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+ if (amdgpu_sriov_vf(adev))
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+ *flags = 0;
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+
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+ /* AMD_CG_SUPPORT_MC_MGCG */
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+ data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));
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+ if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
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+ *flags |= AMD_CG_SUPPORT_MC_MGCG;
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+
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+ /* AMD_CG_SUPPORT_MC_LS */
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+ data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));
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+ if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
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+ *flags |= AMD_CG_SUPPORT_MC_LS;
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+}
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+
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static int mmhub_v1_0_set_powergating_state(void *handle,
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static int mmhub_v1_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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enum amd_powergating_state state)
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{
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{
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@@ -573,6 +592,7 @@ const struct amd_ip_funcs mmhub_v1_0_ip_funcs = {
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.soft_reset = mmhub_v1_0_soft_reset,
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.soft_reset = mmhub_v1_0_soft_reset,
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.set_clockgating_state = mmhub_v1_0_set_clockgating_state,
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.set_clockgating_state = mmhub_v1_0_set_clockgating_state,
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.set_powergating_state = mmhub_v1_0_set_powergating_state,
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.set_powergating_state = mmhub_v1_0_set_powergating_state,
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+ .get_clockgating_state = mmhub_v1_0_get_clockgating_state,
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};
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};
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const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
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const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
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