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@@ -846,6 +846,14 @@ static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
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LRADC_CTRL1);
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mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
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+ /* Enable / disable the divider per requirement */
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+ if (test_bit(chan, &lradc->is_divided))
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+ mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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+ LRADC_CTRL2);
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+ else
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+ mxs_lradc_reg_clear(lradc,
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+ 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
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+
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/* Clean the slot's previous content, then set new one. */
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mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
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LRADC_CTRL4);
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@@ -961,15 +969,11 @@ static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
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if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
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val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
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/* divider by two disabled */
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- writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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- lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
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clear_bit(chan->channel, &lradc->is_divided);
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ret = 0;
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} else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
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val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
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/* divider by two enabled */
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- writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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- lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
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set_bit(chan->channel, &lradc->is_divided);
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ret = 0;
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}
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