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@@ -31,7 +31,118 @@
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#define FM10K_MAX_JUMBO_FRAME_SIZE 15358 /* Maximum supported size 15K */
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#define FM10K_MAX_JUMBO_FRAME_SIZE 15358 /* Maximum supported size 15K */
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+#define MAX_QUEUES FM10K_MAX_QUEUES_PF
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+
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+#define FM10K_MIN_RXD 128
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+#define FM10K_MAX_RXD 4096
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+#define FM10K_DEFAULT_RXD 256
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+
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+#define FM10K_MIN_TXD 128
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+#define FM10K_MAX_TXD 4096
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+#define FM10K_DEFAULT_TXD 256
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+#define FM10K_DEFAULT_TX_WORK 256
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+
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+#define FM10K_RXBUFFER_256 256
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+#define FM10K_RXBUFFER_16384 16384
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+#define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
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+#if PAGE_SIZE <= FM10K_RXBUFFER_16384
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+#define FM10K_RX_BUFSZ (PAGE_SIZE / 2)
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+#else
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+#define FM10K_RX_BUFSZ FM10K_RXBUFFER_16384
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+#endif
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+
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+/* How many Rx Buffers do we bundle into one write to the hardware ? */
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+#define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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+
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+enum fm10k_ring_state_t {
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+ __FM10K_TX_DETECT_HANG,
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+ __FM10K_HANG_CHECK_ARMED,
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+};
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+
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+#define check_for_tx_hang(ring) \
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+ test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
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+#define set_check_for_tx_hang(ring) \
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+ set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
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+#define clear_check_for_tx_hang(ring) \
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+ clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
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+
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+struct fm10k_tx_buffer {
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+ struct fm10k_tx_desc *next_to_watch;
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+ struct sk_buff *skb;
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+ unsigned int bytecount;
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+ u16 gso_segs;
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+ u16 tx_flags;
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+ DEFINE_DMA_UNMAP_ADDR(dma);
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+ DEFINE_DMA_UNMAP_LEN(len);
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+};
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+
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+struct fm10k_rx_buffer {
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+ dma_addr_t dma;
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+ struct page *page;
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+ u32 page_offset;
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+};
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+
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+struct fm10k_queue_stats {
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+ u64 packets;
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+ u64 bytes;
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+};
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+
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+struct fm10k_tx_queue_stats {
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+ u64 restart_queue;
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+ u64 csum_err;
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+ u64 tx_busy;
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+ u64 tx_done_old;
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+};
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+
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+struct fm10k_rx_queue_stats {
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+ u64 alloc_failed;
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+ u64 csum_err;
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+ u64 errors;
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+};
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+
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+struct fm10k_ring {
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+ struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
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+ struct net_device *netdev; /* netdev ring belongs to */
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+ struct device *dev; /* device for DMA mapping */
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+ void *desc; /* descriptor ring memory */
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+ union {
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+ struct fm10k_tx_buffer *tx_buffer;
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+ struct fm10k_rx_buffer *rx_buffer;
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+ };
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+ u32 __iomem *tail;
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+ unsigned long state;
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+ dma_addr_t dma; /* phys. address of descriptor ring */
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+ unsigned int size; /* length in bytes */
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+
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+ u8 queue_index; /* needed for queue management */
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+ u8 reg_idx; /* holds the special value that gets
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+ * the hardware register offset
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+ * associated with this ring, which is
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+ * different for DCB and RSS modes
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+ */
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+ u8 qos_pc; /* priority class of queue */
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+ u16 vid; /* default vlan ID of queue */
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+ u16 count; /* amount of descriptors */
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+
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+ u16 next_to_alloc;
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+ u16 next_to_use;
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+ u16 next_to_clean;
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+
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+ struct fm10k_queue_stats stats;
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+ struct u64_stats_sync syncp;
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+ union {
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+ /* Tx */
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+ struct fm10k_tx_queue_stats tx_stats;
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+ /* Rx */
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+ struct {
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+ struct fm10k_rx_queue_stats rx_stats;
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+ struct sk_buff *skb;
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+ };
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+ };
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+} ____cacheline_internodealigned_in_smp;
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+
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struct fm10k_ring_container {
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struct fm10k_ring_container {
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+ struct fm10k_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u16 work_limit; /* total work allowed per interrupt */
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@@ -46,6 +157,15 @@ struct fm10k_ring_container {
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#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)
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#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)
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+static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
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+{
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+ return &ring->netdev->_tx[ring->queue_index];
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+}
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+
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+/* iterator for handling rings in ring container */
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+#define fm10k_for_each_ring(pos, head) \
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+ for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
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+
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#define MAX_Q_VECTORS 256
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#define MAX_Q_VECTORS 256
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#define MIN_Q_VECTORS 1
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#define MIN_Q_VECTORS 1
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enum fm10k_non_q_vectors {
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enum fm10k_non_q_vectors {
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@@ -68,6 +188,9 @@ struct fm10k_q_vector {
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char name[IFNAMSIZ + 9];
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char name[IFNAMSIZ + 9];
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struct rcu_head rcu; /* to avoid race with update stats on free */
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struct rcu_head rcu; /* to avoid race with update stats on free */
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+
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+ /* for dynamic allocation of rings associated with this q_vector */
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+ struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
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};
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};
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enum fm10k_ring_f_enum {
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enum fm10k_ring_f_enum {
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@@ -113,9 +236,15 @@ struct fm10k_intfc {
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int num_rx_queues;
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int num_rx_queues;
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u16 rx_itr;
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u16 rx_itr;
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+ /* TX */
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+ struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
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+
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u64 rx_overrun_pf;
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u64 rx_overrun_pf;
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u64 rx_overrun_vf;
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u64 rx_overrun_vf;
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+ /* RX */
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+ struct fm10k_ring *rx_ring[MAX_QUEUES];
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+
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/* Queueing vectors */
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/* Queueing vectors */
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struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
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struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
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struct msix_entry *msix_entries;
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struct msix_entry *msix_entries;
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@@ -176,6 +305,65 @@ static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
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return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
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return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
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}
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}
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+/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
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+static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
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+ const u32 stat_err_bits)
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+{
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+ return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
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+}
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+
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+/* fm10k_desc_unused - calculate if we have unused descriptors */
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+static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
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+{
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+ s16 unused = ring->next_to_clean - ring->next_to_use - 1;
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+
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+ return likely(unused < 0) ? unused + ring->count : unused;
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+}
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+
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+#define FM10K_TX_DESC(R, i) \
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+ (&(((struct fm10k_tx_desc *)((R)->desc))[i]))
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+#define FM10K_RX_DESC(R, i) \
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+ (&(((union fm10k_rx_desc *)((R)->desc))[i]))
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+
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+#define FM10K_MAX_TXD_PWR 14
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+#define FM10K_MAX_DATA_PER_TXD (1 << FM10K_MAX_TXD_PWR)
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+
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+/* Tx Descriptors needed, worst case */
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+#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
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+#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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+
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+enum fm10k_tx_flags {
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+ /* Tx offload flags */
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+ FM10K_TX_FLAGS_CSUM = 0x01,
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+};
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+
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+/* This structure is stored as little endian values as that is the native
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+ * format of the Rx descriptor. The ordering of these fields is reversed
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+ * from the actual ftag header to allow for a single bswap to take care
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+ * of placing all of the values in network order
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+ */
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+union fm10k_ftag_info {
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+ __le64 ftag;
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+ struct {
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+ /* dglort and sglort combined into a single 32bit desc read */
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+ __le32 glort;
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+ /* upper 16 bits of vlan are reserved 0 for swpri_type_user */
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+ __le32 vlan;
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+ } d;
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+ struct {
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+ __le16 dglort;
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+ __le16 sglort;
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+ __le16 vlan;
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+ __le16 swpri_type_user;
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+ } w;
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+};
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+
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+struct fm10k_cb {
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+ union fm10k_ftag_info fi;
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+};
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+
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+#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
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+
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/* main */
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/* main */
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extern char fm10k_driver_name[];
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extern char fm10k_driver_name[];
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extern const char fm10k_driver_version[];
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extern const char fm10k_driver_version[];
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