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@@ -53,6 +53,7 @@
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#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
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#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
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/* TI81XX spefic control submodules */
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/* TI81XX spefic control submodules */
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+#define TI81XX_CONTROL_DEVBOOT 0x040
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#define TI81XX_CONTROL_DEVCONF 0x600
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#define TI81XX_CONTROL_DEVCONF 0x600
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/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
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/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
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@@ -246,6 +247,9 @@
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#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
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#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
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#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
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#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
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+/* TI81XX CONTROL_DEVBOOT register offsets */
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+#define TI81XX_CONTROL_STATUS (TI81XX_CONTROL_DEVBOOT + 0x000)
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+
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/* TI81XX CONTROL_DEVCONF register offsets */
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/* TI81XX CONTROL_DEVCONF register offsets */
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#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
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#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
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