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@@ -83,6 +83,7 @@
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#define CFG_RC_CC_MASK 0xf
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#define CFG_STOP_CLOCK BIT(22)
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#define CFG_CLK_ALWAYS_ON BIT(18)
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+#define CFG_CHK_DS BIT(20)
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#define CFG_AUTO_CLK BIT(23)
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#define SD_EMMC_STATUS 0x48
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@@ -408,6 +409,16 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT);
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val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT;
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+ val &= ~CFG_DDR;
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+ if (ios->timing == MMC_TIMING_UHS_DDR50 ||
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+ ios->timing == MMC_TIMING_MMC_DDR52 ||
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+ ios->timing == MMC_TIMING_MMC_HS400)
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+ val |= CFG_DDR;
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+
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+ val &= ~CFG_CHK_DS;
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+ if (ios->timing == MMC_TIMING_MMC_HS400)
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+ val |= CFG_CHK_DS;
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+
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writel(val, host->regs + SD_EMMC_CFG);
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if (val != orig)
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