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@@ -2402,6 +2402,18 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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}
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}
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}
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}
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+static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
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+ uint32_t reg, uint32_t val)
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+{
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+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
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+
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+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
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+ WRITE_DATA_DST_SEL(0)));
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+ amdgpu_ring_write(ring, reg);
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+ amdgpu_ring_write(ring, 0);
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+ amdgpu_ring_write(ring, val);
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+}
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static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
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static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
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{
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{
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@@ -3529,6 +3541,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
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.test_ib = gfx_v6_0_ring_test_ib,
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.test_ib = gfx_v6_0_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.insert_nop = amdgpu_ring_insert_nop,
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.emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
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.emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
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+ .emit_wreg = gfx_v6_0_ring_emit_wreg,
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};
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};
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static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
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static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
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@@ -3554,6 +3567,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
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.test_ring = gfx_v6_0_ring_test_ring,
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.test_ring = gfx_v6_0_ring_test_ring,
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.test_ib = gfx_v6_0_ring_test_ib,
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.test_ib = gfx_v6_0_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.insert_nop = amdgpu_ring_insert_nop,
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+ .emit_wreg = gfx_v6_0_ring_emit_wreg,
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};
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};
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static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
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static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
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