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@@ -19,10 +19,12 @@
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*/
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*/
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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+#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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+#include <linux/uaccess.h>
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#include <asm/cpu_device_id.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/intel-family.h>
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@@ -32,16 +34,106 @@
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static struct pmc_dev pmc;
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static struct pmc_dev pmc;
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+static const struct pmc_bit_map spt_pll_map[] = {
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+ {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
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+ {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
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+ {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
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+ {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
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+ {},
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+};
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+
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+static const struct pmc_bit_map spt_mphy_map[] = {
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+ {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
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+ {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
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+ {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
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+ {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
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+ {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
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+ {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
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+ {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
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+ {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
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+ {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
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+ {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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+ {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
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+ {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
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+ {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
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+ {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
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+ {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
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+ {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
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+ {},
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+};
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+
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+static const struct pmc_bit_map spt_pfear_map[] = {
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+ {"PMC", SPT_PMC_BIT_PMC},
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+ {"OPI-DMI", SPT_PMC_BIT_OPI},
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+ {"SPI / eSPI", SPT_PMC_BIT_SPI},
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+ {"XHCI", SPT_PMC_BIT_XHCI},
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+ {"SPA", SPT_PMC_BIT_SPA},
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+ {"SPB", SPT_PMC_BIT_SPB},
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+ {"SPC", SPT_PMC_BIT_SPC},
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+ {"GBE", SPT_PMC_BIT_GBE},
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+ {"SATA", SPT_PMC_BIT_SATA},
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+ {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
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+ {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
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+ {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
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+ {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
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+ {"RSVD", SPT_PMC_BIT_RSVD_0B},
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+ {"LPSS", SPT_PMC_BIT_LPSS},
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+ {"LPC", SPT_PMC_BIT_LPC},
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+ {"SMB", SPT_PMC_BIT_SMB},
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+ {"ISH", SPT_PMC_BIT_ISH},
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+ {"P2SB", SPT_PMC_BIT_P2SB},
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+ {"DFX", SPT_PMC_BIT_DFX},
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+ {"SCC", SPT_PMC_BIT_SCC},
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+ {"RSVD", SPT_PMC_BIT_RSVD_0C},
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+ {"FUSE", SPT_PMC_BIT_FUSE},
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+ {"CAMERA", SPT_PMC_BIT_CAMREA},
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+ {"RSVD", SPT_PMC_BIT_RSVD_0D},
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+ {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
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+ {"EXI", SPT_PMC_BIT_EXI},
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+ {"CSE", SPT_PMC_BIT_CSE},
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+ {"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
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+ {"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
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+ {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
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+ {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
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+ {"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
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+ {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
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+ {"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
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+ {"RSVD", SPT_PMC_BIT_RSVD_1A},
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+ {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
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+ {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
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+ {"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
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+ {"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
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+ {},
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+};
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+
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+static const struct pmc_reg_map spt_reg_map = {
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+ .pfear_sts = spt_pfear_map,
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+ .mphy_sts = spt_mphy_map,
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+ .pll_sts = spt_pll_map,
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+};
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+
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static const struct pci_device_id pmc_pci_ids[] = {
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static const struct pci_device_id pmc_pci_ids[] = {
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- { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), (kernel_ulong_t)NULL },
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+ { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
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+ (kernel_ulong_t)&spt_reg_map },
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{ 0, },
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{ 0, },
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};
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};
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+static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
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+{
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+ return readb(pmcdev->regbase + offset);
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+}
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+
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static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
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static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
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{
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{
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return readl(pmcdev->regbase + reg_offset);
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return readl(pmcdev->regbase + reg_offset);
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}
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}
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+static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
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+ reg_offset, u32 val)
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+{
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+ writel(val, pmcdev->regbase + reg_offset);
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+}
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+
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static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
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static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
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{
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{
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return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
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return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
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@@ -90,6 +182,245 @@ static int pmc_core_dev_state_get(void *data, u64 *val)
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DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
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DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
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+static int pmc_core_check_read_lock_bit(void)
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+{
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+ struct pmc_dev *pmcdev = &pmc;
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+ u32 value;
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+
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+ value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_CFG_OFFSET);
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+ return test_bit(SPT_PMC_READ_DISABLE_BIT,
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+ (unsigned long *)&value);
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+}
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+
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+#if IS_ENABLED(CONFIG_DEBUG_FS)
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+static void pmc_core_display_map(struct seq_file *s, int index,
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+ u8 pf_reg, const struct pmc_bit_map *pf_map)
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+{
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+ seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
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+ index, pf_map[index].name,
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+ pf_map[index].bit_mask & pf_reg ? "Off" : "On");
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+}
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+
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+static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
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+{
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+ struct pmc_dev *pmcdev = s->private;
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+ const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
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+ u8 pf_regs[NUM_ENTRIES];
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+ int index, iter;
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+
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+ iter = SPT_PMC_XRAM_PPFEAR0A;
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+
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+ for (index = 0; index < NUM_ENTRIES; index++, iter++)
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+ pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
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+
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+ for (index = 0; map[index].name; index++)
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+ pmc_core_display_map(s, index, pf_regs[index / 8], map);
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+
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+ return 0;
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+}
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+
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+static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
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+{
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+ return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
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+}
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+
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+static const struct file_operations pmc_core_ppfear_ops = {
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+ .open = pmc_core_ppfear_sts_open,
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+ .read = seq_read,
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+ .llseek = seq_lseek,
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+ .release = single_release,
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+};
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+
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+/* This function should return link status, 0 means ready */
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+static int pmc_core_mtpmc_link_status(void)
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+{
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+ struct pmc_dev *pmcdev = &pmc;
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+ u32 value;
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+
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+ value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
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+ return test_bit(SPT_PMC_MSG_FULL_STS_BIT,
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+ (unsigned long *)&value);
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+}
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+
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+static int pmc_core_send_msg(u32 *addr_xram)
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+{
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+ struct pmc_dev *pmcdev = &pmc;
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+ u32 dest;
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+ int timeout;
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+
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+ for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
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+ if (pmc_core_mtpmc_link_status() == 0)
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+ break;
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+ msleep(5);
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+ }
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+
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+ if (timeout <= 0 && pmc_core_mtpmc_link_status())
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+ return -EBUSY;
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+
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+ dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
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+ pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
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+ return 0;
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+}
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+
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+static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
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+{
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+ struct pmc_dev *pmcdev = s->private;
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+ const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
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+ u32 mphy_core_reg_low, mphy_core_reg_high;
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+ u32 val_low, val_high;
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+ int index, err = 0;
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+
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+ if (pmcdev->pmc_xram_read_bit) {
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+ seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
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+ return 0;
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+ }
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+
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+ mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
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+ mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
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+
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+ mutex_lock(&pmcdev->lock);
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+
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+ if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
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+ err = -EBUSY;
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+ goto out_unlock;
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+ }
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+
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+ msleep(10);
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+ val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
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+
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+ if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
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+ err = -EBUSY;
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+ goto out_unlock;
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+ }
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+
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+ msleep(10);
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+ val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
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+
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+ for (index = 0; map[index].name && index < 8; index++) {
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+ seq_printf(s, "%-32s\tState: %s\n",
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+ map[index].name,
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+ map[index].bit_mask & val_low ? "Not power gated" :
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+ "Power gated");
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+ }
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+
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+ for (index = 8; map[index].name; index++) {
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+ seq_printf(s, "%-32s\tState: %s\n",
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+ map[index].name,
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+ map[index].bit_mask & val_high ? "Not power gated" :
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+ "Power gated");
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+ }
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+
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+out_unlock:
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+ mutex_unlock(&pmcdev->lock);
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+ return err;
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+}
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+
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+static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
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+{
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+ return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
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+}
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+
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+static const struct file_operations pmc_core_mphy_pg_ops = {
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+ .open = pmc_core_mphy_pg_sts_open,
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+ .read = seq_read,
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+ .llseek = seq_lseek,
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+ .release = single_release,
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+};
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+
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+static int pmc_core_pll_show(struct seq_file *s, void *unused)
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+{
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+ struct pmc_dev *pmcdev = s->private;
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+ const struct pmc_bit_map *map = pmcdev->map->pll_sts;
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+ u32 mphy_common_reg, val;
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+ int index, err = 0;
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+
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+ if (pmcdev->pmc_xram_read_bit) {
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+ seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
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+ return 0;
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+ }
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+
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+ mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
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+ mutex_lock(&pmcdev->lock);
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+
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+ if (pmc_core_send_msg(&mphy_common_reg) != 0) {
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+ err = -EBUSY;
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+ goto out_unlock;
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+ }
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+
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+ /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
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+ msleep(10);
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+ val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
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+
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+ for (index = 0; map[index].name ; index++) {
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+ seq_printf(s, "%-32s\tState: %s\n",
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+ map[index].name,
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+ map[index].bit_mask & val ? "Active" : "Idle");
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+ }
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+
|
|
|
|
+out_unlock:
|
|
|
|
+ mutex_unlock(&pmcdev->lock);
|
|
|
|
+ return err;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int pmc_core_pll_open(struct inode *inode, struct file *file)
|
|
|
|
+{
|
|
|
|
+ return single_open(file, pmc_core_pll_show, inode->i_private);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static const struct file_operations pmc_core_pll_ops = {
|
|
|
|
+ .open = pmc_core_pll_open,
|
|
|
|
+ .read = seq_read,
|
|
|
|
+ .llseek = seq_lseek,
|
|
|
|
+ .release = single_release,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
|
|
|
|
+*userbuf, size_t count, loff_t *ppos)
|
|
|
|
+{
|
|
|
|
+ struct pmc_dev *pmcdev = &pmc;
|
|
|
|
+ u32 val, buf_size, fd;
|
|
|
|
+ int err = 0;
|
|
|
|
+
|
|
|
|
+ buf_size = count < 64 ? count : 64;
|
|
|
|
+ mutex_lock(&pmcdev->lock);
|
|
|
|
+
|
|
|
|
+ if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
|
|
|
|
+ err = -EFAULT;
|
|
|
|
+ goto out_unlock;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (val > NUM_IP_IGN_ALLOWED) {
|
|
|
|
+ err = -EINVAL;
|
|
|
|
+ goto out_unlock;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ fd = pmc_core_reg_read(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET);
|
|
|
|
+ fd |= (1U << val);
|
|
|
|
+ pmc_core_reg_write(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET, fd);
|
|
|
|
+
|
|
|
|
+out_unlock:
|
|
|
|
+ mutex_unlock(&pmcdev->lock);
|
|
|
|
+ return err == 0 ? count : err;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
|
|
|
|
+{
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
|
|
|
|
+{
|
|
|
|
+ return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static const struct file_operations pmc_core_ltr_ignore_ops = {
|
|
|
|
+ .open = pmc_core_ltr_ignore_open,
|
|
|
|
+ .read = seq_read,
|
|
|
|
+ .write = pmc_core_ltr_ignore_write,
|
|
|
|
+ .llseek = seq_lseek,
|
|
|
|
+ .release = single_release,
|
|
|
|
+};
|
|
|
|
+
|
|
static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
|
static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
|
{
|
|
{
|
|
debugfs_remove_recursive(pmcdev->dbgfs_dir);
|
|
debugfs_remove_recursive(pmcdev->dbgfs_dir);
|
|
@@ -106,20 +437,59 @@ static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
|
|
pmcdev->dbgfs_dir = dir;
|
|
pmcdev->dbgfs_dir = dir;
|
|
file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
|
|
file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
|
|
dir, pmcdev, &pmc_core_dev_state);
|
|
dir, pmcdev, &pmc_core_dev_state);
|
|
|
|
+ if (!file)
|
|
|
|
+ goto err;
|
|
|
|
|
|
- if (!file) {
|
|
|
|
- pmc_core_dbgfs_unregister(pmcdev);
|
|
|
|
- return -ENODEV;
|
|
|
|
- }
|
|
|
|
|
|
+ file = debugfs_create_file("pch_ip_power_gating_status",
|
|
|
|
+ S_IFREG | S_IRUGO, dir, pmcdev,
|
|
|
|
+ &pmc_core_ppfear_ops);
|
|
|
|
+ if (!file)
|
|
|
|
+ goto err;
|
|
|
|
+
|
|
|
|
+ file = debugfs_create_file("mphy_core_lanes_power_gating_status",
|
|
|
|
+ S_IFREG | S_IRUGO, dir, pmcdev,
|
|
|
|
+ &pmc_core_mphy_pg_ops);
|
|
|
|
+ if (!file)
|
|
|
|
+ goto err;
|
|
|
|
+
|
|
|
|
+ file = debugfs_create_file("pll_status",
|
|
|
|
+ S_IFREG | S_IRUGO, dir, pmcdev,
|
|
|
|
+ &pmc_core_pll_ops);
|
|
|
|
+ if (!file)
|
|
|
|
+ goto err;
|
|
|
|
+
|
|
|
|
+ file = debugfs_create_file("ltr_ignore",
|
|
|
|
+ S_IFREG | S_IRUGO, dir, pmcdev,
|
|
|
|
+ &pmc_core_ltr_ignore_ops);
|
|
|
|
+
|
|
|
|
+ if (!file)
|
|
|
|
+ goto err;
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
|
|
+err:
|
|
|
|
+ pmc_core_dbgfs_unregister(pmcdev);
|
|
|
|
+ return -ENODEV;
|
|
}
|
|
}
|
|
|
|
+#else
|
|
|
|
+static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
|
|
|
|
+{
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
|
|
|
|
+{
|
|
|
|
+}
|
|
|
|
+#endif /* CONFIG_DEBUG_FS */
|
|
|
|
|
|
static const struct x86_cpu_id intel_pmc_core_ids[] = {
|
|
static const struct x86_cpu_id intel_pmc_core_ids[] = {
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
|
|
(kernel_ulong_t)NULL},
|
|
(kernel_ulong_t)NULL},
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
|
|
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
|
|
(kernel_ulong_t)NULL},
|
|
(kernel_ulong_t)NULL},
|
|
|
|
+ { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
|
|
|
|
+ (kernel_ulong_t)NULL},
|
|
|
|
+ { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
|
|
|
|
+ (kernel_ulong_t)NULL},
|
|
{}
|
|
{}
|
|
};
|
|
};
|
|
|
|
|
|
@@ -128,6 +498,7 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
struct device *ptr_dev = &dev->dev;
|
|
struct device *ptr_dev = &dev->dev;
|
|
struct pmc_dev *pmcdev = &pmc;
|
|
struct pmc_dev *pmcdev = &pmc;
|
|
const struct x86_cpu_id *cpu_id;
|
|
const struct x86_cpu_id *cpu_id;
|
|
|
|
+ const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data;
|
|
int err;
|
|
int err;
|
|
|
|
|
|
cpu_id = x86_match_cpu(intel_pmc_core_ids);
|
|
cpu_id = x86_match_cpu(intel_pmc_core_ids);
|
|
@@ -149,6 +520,7 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
|
|
dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
|
|
return err;
|
|
return err;
|
|
}
|
|
}
|
|
|
|
+ pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
|
|
dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
|
|
dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
|
|
|
|
|
|
pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
|
|
pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
|
|
@@ -159,6 +531,10 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
return -ENOMEM;
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ mutex_init(&pmcdev->lock);
|
|
|
|
+ pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
|
|
|
|
+ pmcdev->map = map;
|
|
|
|
+
|
|
err = pmc_core_dbgfs_register(pmcdev);
|
|
err = pmc_core_dbgfs_register(pmcdev);
|
|
if (err < 0)
|
|
if (err < 0)
|
|
dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
|
|
dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
|