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@@ -546,6 +546,37 @@ void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
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VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
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}
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+static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
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+{
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+ /*
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+ * Base value for VIVS_PM_PULSE_EATER register on models where it
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+ * cannot be read, extracted from vivante kernel driver.
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+ */
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+ u32 pulse_eater = 0x01590880;
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+
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+ if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
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+ etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
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+ pulse_eater |= BIT(23);
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+
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+ }
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+
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+ if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
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+ etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
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+ pulse_eater &= ~BIT(16);
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+ pulse_eater |= BIT(17);
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+ }
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+
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+ if ((gpu->identity.revision > 0x5420) &&
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+ (gpu->identity.features & chipFeatures_PIPE_3D))
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+ {
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+ /* Performance fix: disable internal DFS */
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+ pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
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+ pulse_eater |= BIT(18);
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+ }
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+
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+ gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
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+}
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+
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static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
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{
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u16 prefetch;
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@@ -586,6 +617,9 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
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gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
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}
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+ /* setup the pulse eater */
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+ etnaviv_gpu_setup_pulse_eater(gpu);
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+
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/* setup the MMU */
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etnaviv_iommu_restore(gpu);
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