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@@ -13,9 +13,9 @@
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#ifndef __QCOM_SCM_H
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#define __QCOM_SCM_H
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-extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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-extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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-
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+#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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+#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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+#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
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struct qcom_scm_hdcp_req {
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@@ -23,27 +23,47 @@ struct qcom_scm_hdcp_req {
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u32 val;
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};
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+#if IS_ENABLED(CONFIG_QCOM_SCM)
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+extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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+extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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extern bool qcom_scm_is_available(void);
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-
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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- u32 *resp);
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-
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+ u32 *resp);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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- size_t size);
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+ size_t size);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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- phys_addr_t size);
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+ phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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-
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-#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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-#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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-
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extern void qcom_scm_cpu_power_down(u32 flags);
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-
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-#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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-
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extern u32 qcom_scm_get_version(void);
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+#else
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+static inline
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+int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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+{
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+ return -ENODEV;
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+}
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+static inline
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+int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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+{
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+ return -ENODEV;
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+}
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+static inline bool qcom_scm_is_available(void) { return false; }
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+static inline bool qcom_scm_hdcp_available(void) { return false; }
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+static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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+ u32 *resp) { return -ENODEV; }
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+static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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+static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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+ size_t size) { return -ENODEV; }
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+static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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+ phys_addr_t size) { return -ENODEV; }
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+static inline int
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+qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
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+static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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+static inline void qcom_scm_cpu_power_down(u32 flags) {}
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+static inline u32 qcom_scm_get_version(void) { return 0; }
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+#endif
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#endif
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