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@@ -99,6 +99,17 @@
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/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
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#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
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+struct gpio_regs {
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+ u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
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+ u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
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+ u32 dirm[ZYNQMP_GPIO_MAX_BANK];
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+ u32 outen[ZYNQMP_GPIO_MAX_BANK];
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+ u32 int_en[ZYNQMP_GPIO_MAX_BANK];
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+ u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
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+ u32 int_type[ZYNQMP_GPIO_MAX_BANK];
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+ u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
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+ u32 int_any[ZYNQMP_GPIO_MAX_BANK];
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+};
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/**
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* struct zynq_gpio - gpio device private data structure
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* @chip: instance of the gpio_chip
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@@ -106,6 +117,7 @@
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* @clk: clock resource for this controller
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* @irq: interrupt for the GPIO device
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* @p_data: pointer to platform data
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+ * @context: context registers
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*/
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struct zynq_gpio {
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struct gpio_chip chip;
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@@ -113,6 +125,7 @@ struct zynq_gpio {
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struct clk *clk;
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int irq;
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const struct zynq_platform_data *p_data;
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+ struct gpio_regs context;
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};
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/**
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@@ -560,14 +573,72 @@ static void zynq_gpio_irqhandler(struct irq_desc *desc)
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chained_irq_exit(irqchip, desc);
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}
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+static void zynq_gpio_save_context(struct zynq_gpio *gpio)
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+{
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+ unsigned int bank_num;
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+
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+ for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
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+ gpio->context.datalsw[bank_num] =
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+ readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
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+ gpio->context.datamsw[bank_num] =
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+ readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
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+ gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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+ gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
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+ gpio->context.int_type[bank_num] =
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+ readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
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+ gpio->context.int_polarity[bank_num] =
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+ readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
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+ gpio->context.int_any[bank_num] =
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+ readl_relaxed(gpio->base_addr +
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+ ZYNQ_GPIO_INTANY_OFFSET(bank_num));
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+ }
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+}
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+
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+static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
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+{
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+ unsigned int bank_num;
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+
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+ for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
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+ writel_relaxed(gpio->context.datalsw[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
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+ writel_relaxed(gpio->context.datamsw[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
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+ writel_relaxed(gpio->context.dirm[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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+ writel_relaxed(gpio->context.int_en[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_INTEN_OFFSET(bank_num));
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+ writel_relaxed(gpio->context.int_type[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
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+ writel_relaxed(gpio->context.int_polarity[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
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+ writel_relaxed(gpio->context.int_any[bank_num],
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+ gpio->base_addr +
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+ ZYNQ_GPIO_INTANY_OFFSET(bank_num));
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+ }
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+}
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static int __maybe_unused zynq_gpio_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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int irq = platform_get_irq(pdev, 0);
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struct irq_data *data = irq_get_irq_data(irq);
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+ struct zynq_gpio *gpio = platform_get_drvdata(pdev);
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- if (!irqd_is_wakeup_set(data))
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+ if (!irqd_is_wakeup_set(data)) {
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+ zynq_gpio_save_context(gpio);
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return pm_runtime_force_suspend(dev);
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+ }
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return 0;
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}
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@@ -577,9 +648,14 @@ static int __maybe_unused zynq_gpio_resume(struct device *dev)
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struct platform_device *pdev = to_platform_device(dev);
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int irq = platform_get_irq(pdev, 0);
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struct irq_data *data = irq_get_irq_data(irq);
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+ struct zynq_gpio *gpio = platform_get_drvdata(pdev);
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+ int ret;
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- if (!irqd_is_wakeup_set(data))
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- return pm_runtime_force_resume(dev);
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+ if (!irqd_is_wakeup_set(data)) {
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+ ret = pm_runtime_force_resume(dev);
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+ zynq_gpio_restore_context(gpio);
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+ return ret;
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+ }
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return 0;
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}
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