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@@ -831,11 +831,11 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
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if (IS_ERR(host->clk)) {
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dev_err(&pdev->dev, "Clock failure\n");
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res = -ENOENT;
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- goto err_exit1;
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+ goto enable_wp;
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}
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res = clk_prepare_enable(host->clk);
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if (res)
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- goto err_exit1;
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+ goto enable_wp;
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/* Set NAND IO addresses and command/ready functions */
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chip->IO_ADDR_R = SLC_DATA(host->io_base);
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@@ -874,19 +874,19 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
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GFP_KERNEL);
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if (host->data_buf == NULL) {
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res = -ENOMEM;
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- goto err_exit2;
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+ goto unprepare_clk;
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}
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res = lpc32xx_nand_dma_setup(host);
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if (res) {
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res = -EIO;
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- goto err_exit2;
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+ goto unprepare_clk;
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}
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/* Find NAND device */
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res = nand_scan_ident(mtd, 1, NULL);
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if (res)
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- goto err_exit3;
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+ goto release_dma;
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/* OOB and ECC CPU and DMA work areas */
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host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
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@@ -920,21 +920,23 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
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*/
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res = nand_scan_tail(mtd);
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if (res)
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- goto err_exit3;
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+ goto release_dma;
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mtd->name = "nxp_lpc3220_slc";
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res = mtd_device_register(mtd, host->ncfg->parts,
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host->ncfg->num_parts);
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- if (!res)
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- return res;
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+ if (res)
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+ goto release_nand;
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- nand_release(mtd);
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+ return 0;
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-err_exit3:
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+release_nand:
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+ nand_release(mtd);
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+release_dma:
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dma_release_channel(host->dma_chan);
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-err_exit2:
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+unprepare_clk:
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clk_disable_unprepare(host->clk);
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-err_exit1:
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+enable_wp:
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lpc32xx_wp_enable(host);
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return res;
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