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@@ -85,7 +85,7 @@ MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
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MODULE_LICENSE("Dual BSD/GPL");
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static int ath5k_init(struct ieee80211_hw *hw);
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-static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
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+static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
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bool skip_pcu);
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/* Known SREVs */
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@@ -237,8 +237,8 @@ static const struct ath_ops ath5k_common_ops = {
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static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
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{
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struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
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- struct ath5k_softc *sc = hw->priv;
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- struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
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+ struct ath5k_hw *ah = hw->priv;
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+ struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
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return ath_reg_notifier_apply(wiphy, request, regulatory);
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}
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@@ -288,7 +288,7 @@ ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
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band = IEEE80211_BAND_2GHZ;
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break;
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default:
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- ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
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+ ATH5K_WARN(ah, "bad mode, not copying channels\n");
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return 0;
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}
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@@ -326,51 +326,50 @@ ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
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}
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static void
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-ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
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+ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
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{
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u8 i;
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for (i = 0; i < AR5K_MAX_RATES; i++)
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- sc->rate_idx[b->band][i] = -1;
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+ ah->rate_idx[b->band][i] = -1;
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for (i = 0; i < b->n_bitrates; i++) {
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- sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
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+ ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
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if (b->bitrates[i].hw_value_short)
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- sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
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+ ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
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}
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}
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static int
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ath5k_setup_bands(struct ieee80211_hw *hw)
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{
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- struct ath5k_softc *sc = hw->priv;
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- struct ath5k_hw *ah = sc->ah;
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+ struct ath5k_hw *ah = hw->priv;
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struct ieee80211_supported_band *sband;
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int max_c, count_c = 0;
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int i;
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- BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
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- max_c = ARRAY_SIZE(sc->channels);
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+ BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
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+ max_c = ARRAY_SIZE(ah->channels);
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/* 2GHz band */
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- sband = &sc->sbands[IEEE80211_BAND_2GHZ];
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+ sband = &ah->sbands[IEEE80211_BAND_2GHZ];
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sband->band = IEEE80211_BAND_2GHZ;
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- sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
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+ sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
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- if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
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+ if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
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/* G mode */
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memcpy(sband->bitrates, &ath5k_rates[0],
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sizeof(struct ieee80211_rate) * 12);
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sband->n_bitrates = 12;
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- sband->channels = sc->channels;
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+ sband->channels = ah->channels;
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sband->n_channels = ath5k_setup_channels(ah, sband->channels,
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AR5K_MODE_11G, max_c);
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hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
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count_c = sband->n_channels;
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max_c -= count_c;
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- } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
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+ } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
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/* B mode */
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memcpy(sband->bitrates, &ath5k_rates[0],
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sizeof(struct ieee80211_rate) * 4);
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@@ -389,7 +388,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
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}
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}
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- sband->channels = sc->channels;
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+ sband->channels = ah->channels;
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sband->n_channels = ath5k_setup_channels(ah, sband->channels,
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AR5K_MODE_11B, max_c);
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@@ -397,27 +396,27 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
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count_c = sband->n_channels;
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max_c -= count_c;
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}
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- ath5k_setup_rate_idx(sc, sband);
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+ ath5k_setup_rate_idx(ah, sband);
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/* 5GHz band, A mode */
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- if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
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- sband = &sc->sbands[IEEE80211_BAND_5GHZ];
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+ if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
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+ sband = &ah->sbands[IEEE80211_BAND_5GHZ];
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sband->band = IEEE80211_BAND_5GHZ;
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- sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
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+ sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
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memcpy(sband->bitrates, &ath5k_rates[4],
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sizeof(struct ieee80211_rate) * 8);
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sband->n_bitrates = 8;
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- sband->channels = &sc->channels[count_c];
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+ sband->channels = &ah->channels[count_c];
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sband->n_channels = ath5k_setup_channels(ah, sband->channels,
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AR5K_MODE_11A, max_c);
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hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
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}
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- ath5k_setup_rate_idx(sc, sband);
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+ ath5k_setup_rate_idx(ah, sband);
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- ath5k_debug_dump_bands(sc);
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+ ath5k_debug_dump_bands(ah);
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return 0;
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}
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@@ -427,14 +426,14 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
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* To accomplish this we must first cleanup any pending DMA,
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* then restart stuff after a la ath5k_init.
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*
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- * Called with sc->lock.
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+ * Called with ah->lock.
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*/
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int
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-ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
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+ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
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{
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- ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
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+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
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"channel set, resetting (%u -> %u MHz)\n",
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- sc->curchan->center_freq, chan->center_freq);
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+ ah->curchan->center_freq, chan->center_freq);
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/*
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* To switch channels clear any pending DMA operations;
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@@ -442,7 +441,7 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
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* hardware at the new frequency, and then re-enable
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* the relevant bits of the h/w.
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*/
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- return ath5k_reset(sc, chan, true);
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+ return ath5k_reset(ah, chan, true);
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}
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void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
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@@ -486,10 +485,10 @@ void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
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}
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void
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-ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
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+ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
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struct ieee80211_vif *vif)
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{
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- struct ath_common *common = ath5k_hw_common(sc->ah);
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+ struct ath_common *common = ath5k_hw_common(ah);
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struct ath5k_vif_iter_data iter_data;
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u32 rfilt;
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@@ -508,24 +507,24 @@ ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
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ath5k_vif_iter(&iter_data, vif->addr, vif);
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/* Get list of all active MAC addresses */
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- ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
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+ ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
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&iter_data);
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- memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
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+ memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
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- sc->opmode = iter_data.opmode;
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- if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
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+ ah->opmode = iter_data.opmode;
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+ if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
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/* Nothing active, default to station mode */
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- sc->opmode = NL80211_IFTYPE_STATION;
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+ ah->opmode = NL80211_IFTYPE_STATION;
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- ath5k_hw_set_opmode(sc->ah, sc->opmode);
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- ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
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- sc->opmode, ath_opmode_to_string(sc->opmode));
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+ ath5k_hw_set_opmode(ah, ah->opmode);
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+ ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
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+ ah->opmode, ath_opmode_to_string(ah->opmode));
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if (iter_data.need_set_hw_addr && iter_data.found_active)
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- ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
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+ ath5k_hw_set_lladdr(ah, iter_data.active_mac);
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- if (ath5k_hw_hasbssidmask(sc->ah))
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- ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
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+ if (ath5k_hw_hasbssidmask(ah))
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+ ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
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/* Set up RX Filter */
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if (iter_data.n_stas > 1) {
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@@ -533,16 +532,16 @@ ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
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* different APs, ARPs are not received (most of the time?)
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* Enabling PROMISC appears to fix that problem.
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*/
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- sc->filter_flags |= AR5K_RX_FILTER_PROM;
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+ ah->filter_flags |= AR5K_RX_FILTER_PROM;
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}
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- rfilt = sc->filter_flags;
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- ath5k_hw_set_rx_filter(sc->ah, rfilt);
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- ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
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+ rfilt = ah->filter_flags;
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+ ath5k_hw_set_rx_filter(ah, rfilt);
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+ ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
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}
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static inline int
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-ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
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+ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
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{
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int rix;
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@@ -551,7 +550,7 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
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"hw_rix out of bounds: %x\n", hw_rix))
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return 0;
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- rix = sc->rate_idx[sc->curchan->band][hw_rix];
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+ rix = ah->rate_idx[ah->curchan->band][hw_rix];
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if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
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rix = 0;
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@@ -563,9 +562,9 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
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\***************/
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static
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-struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
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+struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
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{
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- struct ath_common *common = ath5k_hw_common(sc->ah);
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+ struct ath_common *common = ath5k_hw_common(ah);
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struct sk_buff *skb;
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/*
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@@ -577,17 +576,17 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
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GFP_ATOMIC);
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if (!skb) {
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- ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
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+ ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
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common->rx_bufsize);
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return NULL;
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}
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- *skb_addr = dma_map_single(sc->dev,
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+ *skb_addr = dma_map_single(ah->dev,
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skb->data, common->rx_bufsize,
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DMA_FROM_DEVICE);
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- if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
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- ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
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+ if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
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+ ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
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dev_kfree_skb(skb);
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return NULL;
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}
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@@ -595,15 +594,14 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
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}
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static int
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-ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
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+ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
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{
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- struct ath5k_hw *ah = sc->ah;
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struct sk_buff *skb = bf->skb;
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struct ath5k_desc *ds;
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int ret;
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if (!skb) {
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- skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
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+ skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
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if (!skb)
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return -ENOMEM;
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bf->skb = skb;
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@@ -629,13 +627,13 @@ ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
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ds->ds_data = bf->skbaddr;
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ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
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if (ret) {
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- ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
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+ ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
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return ret;
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}
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- if (sc->rxlink != NULL)
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- *sc->rxlink = bf->daddr;
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- sc->rxlink = &ds->ds_link;
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+ if (ah->rxlink != NULL)
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+ *ah->rxlink = bf->daddr;
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+ ah->rxlink = &ds->ds_link;
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return 0;
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}
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@@ -663,10 +661,9 @@ static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
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}
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static int
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-ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
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+ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
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struct ath5k_txq *txq, int padsize)
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{
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- struct ath5k_hw *ah = sc->ah;
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struct ath5k_desc *ds = bf->desc;
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struct sk_buff *skb = bf->skb;
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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@@ -682,10 +679,10 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
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flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
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/* XXX endianness */
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- bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
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+ bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
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DMA_TO_DEVICE);
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- rate = ieee80211_get_tx_rate(sc->hw, info);
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+ rate = ieee80211_get_tx_rate(ah->hw, info);
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if (!rate) {
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ret = -EINVAL;
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goto err_unmap;
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@@ -709,20 +706,20 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
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}
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if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
|
|
|
flags |= AR5K_TXDESC_RTSENA;
|
|
|
- cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
|
|
|
- duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
|
|
|
+ cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
|
|
|
+ duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
|
|
|
info->control.vif, pktlen, info));
|
|
|
}
|
|
|
if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
|
|
|
flags |= AR5K_TXDESC_CTSENA;
|
|
|
- cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
|
|
|
- duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
|
|
|
+ cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
|
|
|
+ duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
|
|
|
info->control.vif, pktlen, info));
|
|
|
}
|
|
|
ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
|
|
|
ieee80211_get_hdrlen_from_skb(skb), padsize,
|
|
|
get_hw_packet_type(skb),
|
|
|
- (sc->power_level * 2),
|
|
|
+ (ah->power_level * 2),
|
|
|
hw_rate,
|
|
|
info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
|
|
|
cts_rate, duration);
|
|
@@ -732,7 +729,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
|
|
|
memset(mrr_rate, 0, sizeof(mrr_rate));
|
|
|
memset(mrr_tries, 0, sizeof(mrr_tries));
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
- rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
|
|
|
+ rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
|
|
|
if (!rate)
|
|
|
break;
|
|
|
|
|
@@ -763,7 +760,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
|
|
|
|
|
|
return 0;
|
|
|
err_unmap:
|
|
|
- dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
|
|
|
+ dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
@@ -772,7 +769,7 @@ err_unmap:
|
|
|
\*******************/
|
|
|
|
|
|
static int
|
|
|
-ath5k_desc_alloc(struct ath5k_softc *sc)
|
|
|
+ath5k_desc_alloc(struct ath5k_hw *ah)
|
|
|
{
|
|
|
struct ath5k_desc *ds;
|
|
|
struct ath5k_buf *bf;
|
|
@@ -781,68 +778,68 @@ ath5k_desc_alloc(struct ath5k_softc *sc)
|
|
|
int ret;
|
|
|
|
|
|
/* allocate descriptors */
|
|
|
- sc->desc_len = sizeof(struct ath5k_desc) *
|
|
|
+ ah->desc_len = sizeof(struct ath5k_desc) *
|
|
|
(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
|
|
|
|
|
|
- sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
|
|
|
- &sc->desc_daddr, GFP_KERNEL);
|
|
|
- if (sc->desc == NULL) {
|
|
|
- ATH5K_ERR(sc, "can't allocate descriptors\n");
|
|
|
+ ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
|
|
|
+ &ah->desc_daddr, GFP_KERNEL);
|
|
|
+ if (ah->desc == NULL) {
|
|
|
+ ATH5K_ERR(ah, "can't allocate descriptors\n");
|
|
|
ret = -ENOMEM;
|
|
|
goto err;
|
|
|
}
|
|
|
- ds = sc->desc;
|
|
|
- da = sc->desc_daddr;
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
|
|
|
- ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
|
|
|
+ ds = ah->desc;
|
|
|
+ da = ah->desc_daddr;
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
|
|
|
+ ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
|
|
|
|
|
|
bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
|
|
|
sizeof(struct ath5k_buf), GFP_KERNEL);
|
|
|
if (bf == NULL) {
|
|
|
- ATH5K_ERR(sc, "can't allocate bufptr\n");
|
|
|
+ ATH5K_ERR(ah, "can't allocate bufptr\n");
|
|
|
ret = -ENOMEM;
|
|
|
goto err_free;
|
|
|
}
|
|
|
- sc->bufptr = bf;
|
|
|
+ ah->bufptr = bf;
|
|
|
|
|
|
- INIT_LIST_HEAD(&sc->rxbuf);
|
|
|
+ INIT_LIST_HEAD(&ah->rxbuf);
|
|
|
for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
|
|
|
bf->desc = ds;
|
|
|
bf->daddr = da;
|
|
|
- list_add_tail(&bf->list, &sc->rxbuf);
|
|
|
+ list_add_tail(&bf->list, &ah->rxbuf);
|
|
|
}
|
|
|
|
|
|
- INIT_LIST_HEAD(&sc->txbuf);
|
|
|
- sc->txbuf_len = ATH_TXBUF;
|
|
|
+ INIT_LIST_HEAD(&ah->txbuf);
|
|
|
+ ah->txbuf_len = ATH_TXBUF;
|
|
|
for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
|
|
|
bf->desc = ds;
|
|
|
bf->daddr = da;
|
|
|
- list_add_tail(&bf->list, &sc->txbuf);
|
|
|
+ list_add_tail(&bf->list, &ah->txbuf);
|
|
|
}
|
|
|
|
|
|
/* beacon buffers */
|
|
|
- INIT_LIST_HEAD(&sc->bcbuf);
|
|
|
+ INIT_LIST_HEAD(&ah->bcbuf);
|
|
|
for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
|
|
|
bf->desc = ds;
|
|
|
bf->daddr = da;
|
|
|
- list_add_tail(&bf->list, &sc->bcbuf);
|
|
|
+ list_add_tail(&bf->list, &ah->bcbuf);
|
|
|
}
|
|
|
|
|
|
return 0;
|
|
|
err_free:
|
|
|
- dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
|
|
|
+ dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
|
|
|
err:
|
|
|
- sc->desc = NULL;
|
|
|
+ ah->desc = NULL;
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
void
|
|
|
-ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
+ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
|
|
|
{
|
|
|
BUG_ON(!bf);
|
|
|
if (!bf->skb)
|
|
|
return;
|
|
|
- dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
|
|
|
+ dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
|
|
|
DMA_TO_DEVICE);
|
|
|
dev_kfree_skb_any(bf->skb);
|
|
|
bf->skb = NULL;
|
|
@@ -851,15 +848,14 @@ ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
}
|
|
|
|
|
|
void
|
|
|
-ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
+ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
|
|
|
BUG_ON(!bf);
|
|
|
if (!bf->skb)
|
|
|
return;
|
|
|
- dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
|
|
|
+ dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
|
|
|
DMA_FROM_DEVICE);
|
|
|
dev_kfree_skb_any(bf->skb);
|
|
|
bf->skb = NULL;
|
|
@@ -868,24 +864,24 @@ ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_desc_free(struct ath5k_softc *sc)
|
|
|
+ath5k_desc_free(struct ath5k_hw *ah)
|
|
|
{
|
|
|
struct ath5k_buf *bf;
|
|
|
|
|
|
- list_for_each_entry(bf, &sc->txbuf, list)
|
|
|
- ath5k_txbuf_free_skb(sc, bf);
|
|
|
- list_for_each_entry(bf, &sc->rxbuf, list)
|
|
|
- ath5k_rxbuf_free_skb(sc, bf);
|
|
|
- list_for_each_entry(bf, &sc->bcbuf, list)
|
|
|
- ath5k_txbuf_free_skb(sc, bf);
|
|
|
+ list_for_each_entry(bf, &ah->txbuf, list)
|
|
|
+ ath5k_txbuf_free_skb(ah, bf);
|
|
|
+ list_for_each_entry(bf, &ah->rxbuf, list)
|
|
|
+ ath5k_rxbuf_free_skb(ah, bf);
|
|
|
+ list_for_each_entry(bf, &ah->bcbuf, list)
|
|
|
+ ath5k_txbuf_free_skb(ah, bf);
|
|
|
|
|
|
/* Free memory associated with all descriptors */
|
|
|
- dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
|
|
|
- sc->desc = NULL;
|
|
|
- sc->desc_daddr = 0;
|
|
|
+ dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
|
|
|
+ ah->desc = NULL;
|
|
|
+ ah->desc_daddr = 0;
|
|
|
|
|
|
- kfree(sc->bufptr);
|
|
|
- sc->bufptr = NULL;
|
|
|
+ kfree(ah->bufptr);
|
|
|
+ ah->bufptr = NULL;
|
|
|
}
|
|
|
|
|
|
|
|
@@ -894,10 +890,9 @@ ath5k_desc_free(struct ath5k_softc *sc)
|
|
|
\**************/
|
|
|
|
|
|
static struct ath5k_txq *
|
|
|
-ath5k_txq_setup(struct ath5k_softc *sc,
|
|
|
+ath5k_txq_setup(struct ath5k_hw *ah,
|
|
|
int qtype, int subtype)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath5k_txq *txq;
|
|
|
struct ath5k_txq_info qi = {
|
|
|
.tqi_subtype = subtype,
|
|
@@ -931,13 +926,13 @@ ath5k_txq_setup(struct ath5k_softc *sc,
|
|
|
*/
|
|
|
return ERR_PTR(qnum);
|
|
|
}
|
|
|
- if (qnum >= ARRAY_SIZE(sc->txqs)) {
|
|
|
- ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
|
|
|
- qnum, ARRAY_SIZE(sc->txqs));
|
|
|
+ if (qnum >= ARRAY_SIZE(ah->txqs)) {
|
|
|
+ ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
|
|
|
+ qnum, ARRAY_SIZE(ah->txqs));
|
|
|
ath5k_hw_release_tx_queue(ah, qnum);
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
}
|
|
|
- txq = &sc->txqs[qnum];
|
|
|
+ txq = &ah->txqs[qnum];
|
|
|
if (!txq->setup) {
|
|
|
txq->qnum = qnum;
|
|
|
txq->link = NULL;
|
|
@@ -949,7 +944,7 @@ ath5k_txq_setup(struct ath5k_softc *sc,
|
|
|
txq->txq_poll_mark = false;
|
|
|
txq->txq_stuck = 0;
|
|
|
}
|
|
|
- return &sc->txqs[qnum];
|
|
|
+ return &ah->txqs[qnum];
|
|
|
}
|
|
|
|
|
|
static int
|
|
@@ -969,18 +964,17 @@ ath5k_beaconq_setup(struct ath5k_hw *ah)
|
|
|
}
|
|
|
|
|
|
static int
|
|
|
-ath5k_beaconq_config(struct ath5k_softc *sc)
|
|
|
+ath5k_beaconq_config(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath5k_txq_info qi;
|
|
|
int ret;
|
|
|
|
|
|
- ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
|
|
|
+ ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
|
|
|
if (ret)
|
|
|
goto err;
|
|
|
|
|
|
- if (sc->opmode == NL80211_IFTYPE_AP ||
|
|
|
- sc->opmode == NL80211_IFTYPE_MESH_POINT) {
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_AP ||
|
|
|
+ ah->opmode == NL80211_IFTYPE_MESH_POINT) {
|
|
|
/*
|
|
|
* Always burst out beacon and CAB traffic
|
|
|
* (aifs = cwmin = cwmax = 0)
|
|
@@ -988,7 +982,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
|
|
|
qi.tqi_aifs = 0;
|
|
|
qi.tqi_cw_min = 0;
|
|
|
qi.tqi_cw_max = 0;
|
|
|
- } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
|
|
|
+ } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
|
|
|
/*
|
|
|
* Adhoc mode; backoff between 0 and (2 * cw_min).
|
|
|
*/
|
|
@@ -997,17 +991,17 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
|
|
|
qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
|
|
|
}
|
|
|
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
|
|
|
"beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
|
|
|
qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
|
|
|
|
|
|
- ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
|
|
|
+ ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
|
|
|
+ ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
|
|
|
"hardware queue!\n", __func__);
|
|
|
goto err;
|
|
|
}
|
|
|
- ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
|
|
|
+ ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
|
|
|
if (ret)
|
|
|
goto err;
|
|
|
|
|
@@ -1016,7 +1010,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
|
|
|
if (ret)
|
|
|
goto err;
|
|
|
|
|
|
- qi.tqi_ready_time = (sc->bintval * 80) / 100;
|
|
|
+ qi.tqi_ready_time = (ah->bintval * 80) / 100;
|
|
|
ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
|
|
|
if (ret)
|
|
|
goto err;
|
|
@@ -1029,7 +1023,7 @@ err:
|
|
|
/**
|
|
|
* ath5k_drain_tx_buffs - Empty tx buffers
|
|
|
*
|
|
|
- * @sc The &struct ath5k_softc
|
|
|
+ * @ah The &struct ath5k_hw
|
|
|
*
|
|
|
* Empty tx buffers from all queues in preparation
|
|
|
* of a reset or during shutdown.
|
|
@@ -1038,26 +1032,26 @@ err:
|
|
|
* we do not need to block ath5k_tx_tasklet
|
|
|
*/
|
|
|
static void
|
|
|
-ath5k_drain_tx_buffs(struct ath5k_softc *sc)
|
|
|
+ath5k_drain_tx_buffs(struct ath5k_hw *ah)
|
|
|
{
|
|
|
struct ath5k_txq *txq;
|
|
|
struct ath5k_buf *bf, *bf0;
|
|
|
int i;
|
|
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
|
|
|
- if (sc->txqs[i].setup) {
|
|
|
- txq = &sc->txqs[i];
|
|
|
+ for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
|
|
|
+ if (ah->txqs[i].setup) {
|
|
|
+ txq = &ah->txqs[i];
|
|
|
spin_lock_bh(&txq->lock);
|
|
|
list_for_each_entry_safe(bf, bf0, &txq->q, list) {
|
|
|
- ath5k_debug_printtxbuf(sc, bf);
|
|
|
+ ath5k_debug_printtxbuf(ah, bf);
|
|
|
|
|
|
- ath5k_txbuf_free_skb(sc, bf);
|
|
|
+ ath5k_txbuf_free_skb(ah, bf);
|
|
|
|
|
|
- spin_lock_bh(&sc->txbuflock);
|
|
|
- list_move_tail(&bf->list, &sc->txbuf);
|
|
|
- sc->txbuf_len++;
|
|
|
+ spin_lock_bh(&ah->txbuflock);
|
|
|
+ list_move_tail(&bf->list, &ah->txbuf);
|
|
|
+ ah->txbuf_len++;
|
|
|
txq->txq_len--;
|
|
|
- spin_unlock_bh(&sc->txbuflock);
|
|
|
+ spin_unlock_bh(&ah->txbuflock);
|
|
|
}
|
|
|
txq->link = NULL;
|
|
|
txq->txq_poll_mark = false;
|
|
@@ -1067,14 +1061,14 @@ ath5k_drain_tx_buffs(struct ath5k_softc *sc)
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_txq_release(struct ath5k_softc *sc)
|
|
|
+ath5k_txq_release(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_txq *txq = sc->txqs;
|
|
|
+ struct ath5k_txq *txq = ah->txqs;
|
|
|
unsigned int i;
|
|
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
|
|
|
+ for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
|
|
|
if (txq->setup) {
|
|
|
- ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
|
|
|
+ ath5k_hw_release_tx_queue(ah, txq->qnum);
|
|
|
txq->setup = false;
|
|
|
}
|
|
|
}
|
|
@@ -1088,33 +1082,32 @@ ath5k_txq_release(struct ath5k_softc *sc)
|
|
|
* Enable the receive h/w following a reset.
|
|
|
*/
|
|
|
static int
|
|
|
-ath5k_rx_start(struct ath5k_softc *sc)
|
|
|
+ath5k_rx_start(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
struct ath5k_buf *bf;
|
|
|
int ret;
|
|
|
|
|
|
common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
|
|
|
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
|
|
|
common->cachelsz, common->rx_bufsize);
|
|
|
|
|
|
- spin_lock_bh(&sc->rxbuflock);
|
|
|
- sc->rxlink = NULL;
|
|
|
- list_for_each_entry(bf, &sc->rxbuf, list) {
|
|
|
- ret = ath5k_rxbuf_setup(sc, bf);
|
|
|
+ spin_lock_bh(&ah->rxbuflock);
|
|
|
+ ah->rxlink = NULL;
|
|
|
+ list_for_each_entry(bf, &ah->rxbuf, list) {
|
|
|
+ ret = ath5k_rxbuf_setup(ah, bf);
|
|
|
if (ret != 0) {
|
|
|
- spin_unlock_bh(&sc->rxbuflock);
|
|
|
+ spin_unlock_bh(&ah->rxbuflock);
|
|
|
goto err;
|
|
|
}
|
|
|
}
|
|
|
- bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
|
|
|
+ bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
|
|
|
ath5k_hw_set_rxdp(ah, bf->daddr);
|
|
|
- spin_unlock_bh(&sc->rxbuflock);
|
|
|
+ spin_unlock_bh(&ah->rxbuflock);
|
|
|
|
|
|
ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
|
|
|
- ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
|
|
|
+ ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
|
|
|
ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
|
|
|
|
|
|
return 0;
|
|
@@ -1130,21 +1123,19 @@ err:
|
|
|
* does.
|
|
|
*/
|
|
|
static void
|
|
|
-ath5k_rx_stop(struct ath5k_softc *sc)
|
|
|
+ath5k_rx_stop(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
|
|
|
ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
|
|
|
ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
|
|
|
|
|
|
- ath5k_debug_printrxbuffs(sc, ah);
|
|
|
+ ath5k_debug_printrxbuffs(ah);
|
|
|
}
|
|
|
|
|
|
static unsigned int
|
|
|
-ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
+ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
|
|
|
struct ath5k_rx_status *rs)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
struct ieee80211_hdr *hdr = (void *)skb->data;
|
|
|
unsigned int keyix, hlen;
|
|
@@ -1171,10 +1162,10 @@ ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
|
|
|
|
|
|
static void
|
|
|
-ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
+ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
|
|
|
struct ieee80211_rx_status *rxs)
|
|
|
{
|
|
|
- struct ath_common *common = ath5k_hw_common(sc->ah);
|
|
|
+ struct ath_common *common = ath5k_hw_common(ah);
|
|
|
u64 tsf, bc_tstamp;
|
|
|
u32 hw_tu;
|
|
|
struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
|
|
@@ -1187,11 +1178,11 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
* have updated the local TSF. We have to work around various
|
|
|
* hardware bugs, though...
|
|
|
*/
|
|
|
- tsf = ath5k_hw_get_tsf64(sc->ah);
|
|
|
+ tsf = ath5k_hw_get_tsf64(ah);
|
|
|
bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
|
|
|
hw_tu = TSF_TO_TU(tsf);
|
|
|
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
|
|
|
(unsigned long long)bc_tstamp,
|
|
|
(unsigned long long)rxs->mactime,
|
|
@@ -1210,7 +1201,7 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
* received, not like mac80211 which defines it at the start.
|
|
|
*/
|
|
|
if (bc_tstamp > rxs->mactime) {
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"fixing mactime from %llx to %llx\n",
|
|
|
(unsigned long long)rxs->mactime,
|
|
|
(unsigned long long)tsf);
|
|
@@ -1223,25 +1214,24 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
* beacons. This also takes care of synchronizing beacon sending
|
|
|
* times with other stations.
|
|
|
*/
|
|
|
- if (hw_tu >= sc->nexttbtt)
|
|
|
- ath5k_beacon_update_timers(sc, bc_tstamp);
|
|
|
+ if (hw_tu >= ah->nexttbtt)
|
|
|
+ ath5k_beacon_update_timers(ah, bc_tstamp);
|
|
|
|
|
|
/* Check if the beacon timers are still correct, because a TSF
|
|
|
* update might have created a window between them - for a
|
|
|
* longer description see the comment of this function: */
|
|
|
- if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
|
|
|
- ath5k_beacon_update_timers(sc, bc_tstamp);
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
|
|
|
+ ath5k_beacon_update_timers(ah, bc_tstamp);
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"fixed beacon timers after beacon receive\n");
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
|
|
|
+ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
|
|
|
{
|
|
|
struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
|
|
|
/* only beacons from our BSSID */
|
|
@@ -1323,7 +1313,7 @@ static int ath5k_remove_padding(struct sk_buff *skb)
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
+ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
|
|
|
struct ath5k_rx_status *rs)
|
|
|
{
|
|
|
struct ieee80211_rx_status *rxs;
|
|
@@ -1356,37 +1346,37 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
* impossible to comply to that. This affects IBSS merge only
|
|
|
* right now, so it's not too bad...
|
|
|
*/
|
|
|
- rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
|
|
|
+ rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
|
|
|
rxs->flag |= RX_FLAG_MACTIME_MPDU;
|
|
|
|
|
|
- rxs->freq = sc->curchan->center_freq;
|
|
|
- rxs->band = sc->curchan->band;
|
|
|
+ rxs->freq = ah->curchan->center_freq;
|
|
|
+ rxs->band = ah->curchan->band;
|
|
|
|
|
|
- rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
|
|
|
+ rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
|
|
|
|
|
|
rxs->antenna = rs->rs_antenna;
|
|
|
|
|
|
if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
|
|
|
- sc->stats.antenna_rx[rs->rs_antenna]++;
|
|
|
+ ah->stats.antenna_rx[rs->rs_antenna]++;
|
|
|
else
|
|
|
- sc->stats.antenna_rx[0]++; /* invalid */
|
|
|
+ ah->stats.antenna_rx[0]++; /* invalid */
|
|
|
|
|
|
- rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
|
|
|
- rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
|
|
|
+ rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
|
|
|
+ rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
|
|
|
|
|
|
if (rxs->rate_idx >= 0 && rs->rs_rate ==
|
|
|
- sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
|
|
|
+ ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
|
|
|
rxs->flag |= RX_FLAG_SHORTPRE;
|
|
|
|
|
|
- trace_ath5k_rx(sc, skb);
|
|
|
+ trace_ath5k_rx(ah, skb);
|
|
|
|
|
|
- ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
|
|
|
+ ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
|
|
|
|
|
|
/* check beacons in IBSS mode */
|
|
|
- if (sc->opmode == NL80211_IFTYPE_ADHOC)
|
|
|
- ath5k_check_ibss_tsf(sc, skb, rxs);
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_ADHOC)
|
|
|
+ ath5k_check_ibss_tsf(ah, skb, rxs);
|
|
|
|
|
|
- ieee80211_rx(sc->hw, skb);
|
|
|
+ ieee80211_rx(ah->hw, skb);
|
|
|
}
|
|
|
|
|
|
/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
|
|
@@ -1395,20 +1385,20 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
* statistics. Return true if we want this frame, false if not.
|
|
|
*/
|
|
|
static bool
|
|
|
-ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
|
|
|
+ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
|
|
|
{
|
|
|
- sc->stats.rx_all_count++;
|
|
|
- sc->stats.rx_bytes_count += rs->rs_datalen;
|
|
|
+ ah->stats.rx_all_count++;
|
|
|
+ ah->stats.rx_bytes_count += rs->rs_datalen;
|
|
|
|
|
|
if (unlikely(rs->rs_status)) {
|
|
|
if (rs->rs_status & AR5K_RXERR_CRC)
|
|
|
- sc->stats.rxerr_crc++;
|
|
|
+ ah->stats.rxerr_crc++;
|
|
|
if (rs->rs_status & AR5K_RXERR_FIFO)
|
|
|
- sc->stats.rxerr_fifo++;
|
|
|
+ ah->stats.rxerr_fifo++;
|
|
|
if (rs->rs_status & AR5K_RXERR_PHY) {
|
|
|
- sc->stats.rxerr_phy++;
|
|
|
+ ah->stats.rxerr_phy++;
|
|
|
if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
|
|
|
- sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
|
|
|
+ ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
|
|
|
return false;
|
|
|
}
|
|
|
if (rs->rs_status & AR5K_RXERR_DECRYPT) {
|
|
@@ -1422,13 +1412,13 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
|
|
|
*
|
|
|
* XXX do key cache faulting
|
|
|
*/
|
|
|
- sc->stats.rxerr_decrypt++;
|
|
|
+ ah->stats.rxerr_decrypt++;
|
|
|
if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
|
|
|
!(rs->rs_status & AR5K_RXERR_CRC))
|
|
|
return true;
|
|
|
}
|
|
|
if (rs->rs_status & AR5K_RXERR_MIC) {
|
|
|
- sc->stats.rxerr_mic++;
|
|
|
+ ah->stats.rxerr_mic++;
|
|
|
return true;
|
|
|
}
|
|
|
|
|
@@ -1438,26 +1428,26 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
|
|
|
}
|
|
|
|
|
|
if (unlikely(rs->rs_more)) {
|
|
|
- sc->stats.rxerr_jumbo++;
|
|
|
+ ah->stats.rxerr_jumbo++;
|
|
|
return false;
|
|
|
}
|
|
|
return true;
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_set_current_imask(struct ath5k_softc *sc)
|
|
|
+ath5k_set_current_imask(struct ath5k_hw *ah)
|
|
|
{
|
|
|
enum ath5k_int imask;
|
|
|
unsigned long flags;
|
|
|
|
|
|
- spin_lock_irqsave(&sc->irqlock, flags);
|
|
|
- imask = sc->imask;
|
|
|
- if (sc->rx_pending)
|
|
|
+ spin_lock_irqsave(&ah->irqlock, flags);
|
|
|
+ imask = ah->imask;
|
|
|
+ if (ah->rx_pending)
|
|
|
imask &= ~AR5K_INT_RX_ALL;
|
|
|
- if (sc->tx_pending)
|
|
|
+ if (ah->tx_pending)
|
|
|
imask &= ~AR5K_INT_TX_ALL;
|
|
|
- ath5k_hw_set_imr(sc->ah, imask);
|
|
|
- spin_unlock_irqrestore(&sc->irqlock, flags);
|
|
|
+ ath5k_hw_set_imr(ah, imask);
|
|
|
+ spin_unlock_irqrestore(&ah->irqlock, flags);
|
|
|
}
|
|
|
|
|
|
static void
|
|
@@ -1466,39 +1456,38 @@ ath5k_tasklet_rx(unsigned long data)
|
|
|
struct ath5k_rx_status rs = {};
|
|
|
struct sk_buff *skb, *next_skb;
|
|
|
dma_addr_t next_skb_addr;
|
|
|
- struct ath5k_softc *sc = (void *)data;
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
+ struct ath5k_hw *ah = (void *)data;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
struct ath5k_buf *bf;
|
|
|
struct ath5k_desc *ds;
|
|
|
int ret;
|
|
|
|
|
|
- spin_lock(&sc->rxbuflock);
|
|
|
- if (list_empty(&sc->rxbuf)) {
|
|
|
- ATH5K_WARN(sc, "empty rx buf pool\n");
|
|
|
+ spin_lock(&ah->rxbuflock);
|
|
|
+ if (list_empty(&ah->rxbuf)) {
|
|
|
+ ATH5K_WARN(ah, "empty rx buf pool\n");
|
|
|
goto unlock;
|
|
|
}
|
|
|
do {
|
|
|
- bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
|
|
|
+ bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
|
|
|
BUG_ON(bf->skb == NULL);
|
|
|
skb = bf->skb;
|
|
|
ds = bf->desc;
|
|
|
|
|
|
/* bail if HW is still using self-linked descriptor */
|
|
|
- if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
|
|
|
+ if (ath5k_hw_get_rxdp(ah) == bf->daddr)
|
|
|
break;
|
|
|
|
|
|
- ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
|
|
|
+ ret = ah->ah_proc_rx_desc(ah, ds, &rs);
|
|
|
if (unlikely(ret == -EINPROGRESS))
|
|
|
break;
|
|
|
else if (unlikely(ret)) {
|
|
|
- ATH5K_ERR(sc, "error in processing rx descriptor\n");
|
|
|
- sc->stats.rxerr_proc++;
|
|
|
+ ATH5K_ERR(ah, "error in processing rx descriptor\n");
|
|
|
+ ah->stats.rxerr_proc++;
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
- if (ath5k_receive_frame_ok(sc, &rs)) {
|
|
|
- next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
|
|
|
+ if (ath5k_receive_frame_ok(ah, &rs)) {
|
|
|
+ next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
|
|
|
|
|
|
/*
|
|
|
* If we can't replace bf->skb with a new skb under
|
|
@@ -1507,24 +1496,24 @@ ath5k_tasklet_rx(unsigned long data)
|
|
|
if (!next_skb)
|
|
|
goto next;
|
|
|
|
|
|
- dma_unmap_single(sc->dev, bf->skbaddr,
|
|
|
+ dma_unmap_single(ah->dev, bf->skbaddr,
|
|
|
common->rx_bufsize,
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
|
skb_put(skb, rs.rs_datalen);
|
|
|
|
|
|
- ath5k_receive_frame(sc, skb, &rs);
|
|
|
+ ath5k_receive_frame(ah, skb, &rs);
|
|
|
|
|
|
bf->skb = next_skb;
|
|
|
bf->skbaddr = next_skb_addr;
|
|
|
}
|
|
|
next:
|
|
|
- list_move_tail(&bf->list, &sc->rxbuf);
|
|
|
- } while (ath5k_rxbuf_setup(sc, bf) == 0);
|
|
|
+ list_move_tail(&bf->list, &ah->rxbuf);
|
|
|
+ } while (ath5k_rxbuf_setup(ah, bf) == 0);
|
|
|
unlock:
|
|
|
- spin_unlock(&sc->rxbuflock);
|
|
|
- sc->rx_pending = false;
|
|
|
- ath5k_set_current_imask(sc);
|
|
|
+ spin_unlock(&ah->rxbuflock);
|
|
|
+ ah->rx_pending = false;
|
|
|
+ ath5k_set_current_imask(ah);
|
|
|
}
|
|
|
|
|
|
|
|
@@ -1536,12 +1525,12 @@ void
|
|
|
ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
|
struct ath5k_txq *txq)
|
|
|
{
|
|
|
- struct ath5k_softc *sc = hw->priv;
|
|
|
+ struct ath5k_hw *ah = hw->priv;
|
|
|
struct ath5k_buf *bf;
|
|
|
unsigned long flags;
|
|
|
int padsize;
|
|
|
|
|
|
- trace_ath5k_tx(sc, skb, txq);
|
|
|
+ trace_ath5k_tx(ah, skb, txq);
|
|
|
|
|
|
/*
|
|
|
* The hardware expects the header padded to 4 byte boundaries.
|
|
@@ -1549,7 +1538,7 @@ ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
|
*/
|
|
|
padsize = ath5k_add_padding(skb);
|
|
|
if (padsize < 0) {
|
|
|
- ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
|
|
|
+ ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
|
|
|
" headroom to pad");
|
|
|
goto drop_packet;
|
|
|
}
|
|
@@ -1558,28 +1547,28 @@ ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
|
txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
|
|
|
ieee80211_stop_queue(hw, txq->qnum);
|
|
|
|
|
|
- spin_lock_irqsave(&sc->txbuflock, flags);
|
|
|
- if (list_empty(&sc->txbuf)) {
|
|
|
- ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
|
|
|
- spin_unlock_irqrestore(&sc->txbuflock, flags);
|
|
|
+ spin_lock_irqsave(&ah->txbuflock, flags);
|
|
|
+ if (list_empty(&ah->txbuf)) {
|
|
|
+ ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
|
|
|
+ spin_unlock_irqrestore(&ah->txbuflock, flags);
|
|
|
ieee80211_stop_queues(hw);
|
|
|
goto drop_packet;
|
|
|
}
|
|
|
- bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
|
|
|
+ bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
|
|
|
list_del(&bf->list);
|
|
|
- sc->txbuf_len--;
|
|
|
- if (list_empty(&sc->txbuf))
|
|
|
+ ah->txbuf_len--;
|
|
|
+ if (list_empty(&ah->txbuf))
|
|
|
ieee80211_stop_queues(hw);
|
|
|
- spin_unlock_irqrestore(&sc->txbuflock, flags);
|
|
|
+ spin_unlock_irqrestore(&ah->txbuflock, flags);
|
|
|
|
|
|
bf->skb = skb;
|
|
|
|
|
|
- if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
|
|
|
+ if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
|
|
|
bf->skb = NULL;
|
|
|
- spin_lock_irqsave(&sc->txbuflock, flags);
|
|
|
- list_add_tail(&bf->list, &sc->txbuf);
|
|
|
- sc->txbuf_len++;
|
|
|
- spin_unlock_irqrestore(&sc->txbuflock, flags);
|
|
|
+ spin_lock_irqsave(&ah->txbuflock, flags);
|
|
|
+ list_add_tail(&bf->list, &ah->txbuf);
|
|
|
+ ah->txbuf_len++;
|
|
|
+ spin_unlock_irqrestore(&ah->txbuflock, flags);
|
|
|
goto drop_packet;
|
|
|
}
|
|
|
return;
|
|
@@ -1589,15 +1578,15 @@ drop_packet:
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
+ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
|
|
|
struct ath5k_txq *txq, struct ath5k_tx_status *ts)
|
|
|
{
|
|
|
struct ieee80211_tx_info *info;
|
|
|
u8 tries[3];
|
|
|
int i;
|
|
|
|
|
|
- sc->stats.tx_all_count++;
|
|
|
- sc->stats.tx_bytes_count += skb->len;
|
|
|
+ ah->stats.tx_all_count++;
|
|
|
+ ah->stats.tx_bytes_count += skb->len;
|
|
|
info = IEEE80211_SKB_CB(skb);
|
|
|
|
|
|
tries[0] = info->status.rates[0].count;
|
|
@@ -1617,15 +1606,15 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
info->status.rates[ts->ts_final_idx + 1].idx = -1;
|
|
|
|
|
|
if (unlikely(ts->ts_status)) {
|
|
|
- sc->stats.ack_fail++;
|
|
|
+ ah->stats.ack_fail++;
|
|
|
if (ts->ts_status & AR5K_TXERR_FILT) {
|
|
|
info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
|
|
|
- sc->stats.txerr_filt++;
|
|
|
+ ah->stats.txerr_filt++;
|
|
|
}
|
|
|
if (ts->ts_status & AR5K_TXERR_XRETRY)
|
|
|
- sc->stats.txerr_retry++;
|
|
|
+ ah->stats.txerr_retry++;
|
|
|
if (ts->ts_status & AR5K_TXERR_FIFO)
|
|
|
- sc->stats.txerr_fifo++;
|
|
|
+ ah->stats.txerr_fifo++;
|
|
|
} else {
|
|
|
info->flags |= IEEE80211_TX_STAT_ACK;
|
|
|
info->status.ack_signal = ts->ts_rssi;
|
|
@@ -1641,16 +1630,16 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
|
|
|
ath5k_remove_padding(skb);
|
|
|
|
|
|
if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
|
|
|
- sc->stats.antenna_tx[ts->ts_antenna]++;
|
|
|
+ ah->stats.antenna_tx[ts->ts_antenna]++;
|
|
|
else
|
|
|
- sc->stats.antenna_tx[0]++; /* invalid */
|
|
|
+ ah->stats.antenna_tx[0]++; /* invalid */
|
|
|
|
|
|
- trace_ath5k_tx_complete(sc, skb, txq, ts);
|
|
|
- ieee80211_tx_status(sc->hw, skb);
|
|
|
+ trace_ath5k_tx_complete(ah, skb, txq, ts);
|
|
|
+ ieee80211_tx_status(ah->hw, skb);
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
|
|
|
+ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
|
|
|
{
|
|
|
struct ath5k_tx_status ts = {};
|
|
|
struct ath5k_buf *bf, *bf0;
|
|
@@ -1667,11 +1656,11 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
|
|
|
if (bf->skb != NULL) {
|
|
|
ds = bf->desc;
|
|
|
|
|
|
- ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
|
|
|
+ ret = ah->ah_proc_tx_desc(ah, ds, &ts);
|
|
|
if (unlikely(ret == -EINPROGRESS))
|
|
|
break;
|
|
|
else if (unlikely(ret)) {
|
|
|
- ATH5K_ERR(sc,
|
|
|
+ ATH5K_ERR(ah,
|
|
|
"error %d while processing "
|
|
|
"queue %u\n", ret, txq->qnum);
|
|
|
break;
|
|
@@ -1680,9 +1669,9 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
|
|
|
skb = bf->skb;
|
|
|
bf->skb = NULL;
|
|
|
|
|
|
- dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
|
|
|
+ dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
|
|
|
DMA_TO_DEVICE);
|
|
|
- ath5k_tx_frame_completed(sc, skb, txq, &ts);
|
|
|
+ ath5k_tx_frame_completed(ah, skb, txq, &ts);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -1691,31 +1680,31 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
|
|
|
* host memory and moved on.
|
|
|
* Always keep the last descriptor to avoid HW races...
|
|
|
*/
|
|
|
- if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
|
|
|
- spin_lock(&sc->txbuflock);
|
|
|
- list_move_tail(&bf->list, &sc->txbuf);
|
|
|
- sc->txbuf_len++;
|
|
|
+ if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
|
|
|
+ spin_lock(&ah->txbuflock);
|
|
|
+ list_move_tail(&bf->list, &ah->txbuf);
|
|
|
+ ah->txbuf_len++;
|
|
|
txq->txq_len--;
|
|
|
- spin_unlock(&sc->txbuflock);
|
|
|
+ spin_unlock(&ah->txbuflock);
|
|
|
}
|
|
|
}
|
|
|
spin_unlock(&txq->lock);
|
|
|
if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
|
|
|
- ieee80211_wake_queue(sc->hw, txq->qnum);
|
|
|
+ ieee80211_wake_queue(ah->hw, txq->qnum);
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
ath5k_tasklet_tx(unsigned long data)
|
|
|
{
|
|
|
int i;
|
|
|
- struct ath5k_softc *sc = (void *)data;
|
|
|
+ struct ath5k_hw *ah = (void *)data;
|
|
|
|
|
|
for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
|
|
|
- if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
|
|
|
- ath5k_tx_processq(sc, &sc->txqs[i]);
|
|
|
+ if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
|
|
|
+ ath5k_tx_processq(ah, &ah->txqs[i]);
|
|
|
|
|
|
- sc->tx_pending = false;
|
|
|
- ath5k_set_current_imask(sc);
|
|
|
+ ah->tx_pending = false;
|
|
|
+ ath5k_set_current_imask(ah);
|
|
|
}
|
|
|
|
|
|
|
|
@@ -1727,25 +1716,24 @@ ath5k_tasklet_tx(unsigned long data)
|
|
|
* Setup the beacon frame for transmit.
|
|
|
*/
|
|
|
static int
|
|
|
-ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
+ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
|
|
|
{
|
|
|
struct sk_buff *skb = bf->skb;
|
|
|
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath5k_desc *ds;
|
|
|
int ret = 0;
|
|
|
u8 antenna;
|
|
|
u32 flags;
|
|
|
const int padsize = 0;
|
|
|
|
|
|
- bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
|
|
|
+ bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
|
|
|
DMA_TO_DEVICE);
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
|
|
|
"skbaddr %llx\n", skb, skb->data, skb->len,
|
|
|
(unsigned long long)bf->skbaddr);
|
|
|
|
|
|
- if (dma_mapping_error(sc->dev, bf->skbaddr)) {
|
|
|
- ATH5K_ERR(sc, "beacon DMA mapping failed\n");
|
|
|
+ if (dma_mapping_error(ah->dev, bf->skbaddr)) {
|
|
|
+ ATH5K_ERR(ah, "beacon DMA mapping failed\n");
|
|
|
return -EIO;
|
|
|
}
|
|
|
|
|
@@ -1753,7 +1741,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
antenna = ah->ah_tx_ant;
|
|
|
|
|
|
flags = AR5K_TXDESC_NOACK;
|
|
|
- if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
|
|
|
ds->ds_link = bf->daddr; /* self-linked */
|
|
|
flags |= AR5K_TXDESC_VEOL;
|
|
|
} else
|
|
@@ -1778,7 +1766,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
* on all of them.
|
|
|
*/
|
|
|
if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
|
|
|
- antenna = sc->bsent & 4 ? 2 : 1;
|
|
|
+ antenna = ah->bsent & 4 ? 2 : 1;
|
|
|
|
|
|
|
|
|
/* FIXME: If we are in g mode and rate is a CCK rate
|
|
@@ -1787,8 +1775,8 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
ds->ds_data = bf->skbaddr;
|
|
|
ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
|
|
|
ieee80211_get_hdrlen_from_skb(skb), padsize,
|
|
|
- AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
|
|
|
- ieee80211_get_tx_rate(sc->hw, info)->hw_value,
|
|
|
+ AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
|
|
|
+ ieee80211_get_tx_rate(ah->hw, info)->hw_value,
|
|
|
1, AR5K_TXKEYIX_INVALID,
|
|
|
antenna, flags, 0, 0);
|
|
|
if (ret)
|
|
@@ -1796,7 +1784,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
|
|
|
|
|
|
return 0;
|
|
|
err_unmap:
|
|
|
- dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
|
|
|
+ dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
@@ -1811,7 +1799,7 @@ int
|
|
|
ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
|
|
|
{
|
|
|
int ret;
|
|
|
- struct ath5k_softc *sc = hw->priv;
|
|
|
+ struct ath5k_hw *ah = hw->priv;
|
|
|
struct ath5k_vif *avf = (void *)vif->drv_priv;
|
|
|
struct sk_buff *skb;
|
|
|
|
|
@@ -1827,9 +1815,9 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
|
|
|
goto out;
|
|
|
}
|
|
|
|
|
|
- ath5k_txbuf_free_skb(sc, avf->bbuf);
|
|
|
+ ath5k_txbuf_free_skb(ah, avf->bbuf);
|
|
|
avf->bbuf->skb = skb;
|
|
|
- ret = ath5k_beacon_setup(sc, avf->bbuf);
|
|
|
+ ret = ath5k_beacon_setup(ah, avf->bbuf);
|
|
|
if (ret)
|
|
|
avf->bbuf->skb = NULL;
|
|
|
out:
|
|
@@ -1845,15 +1833,14 @@ out:
|
|
|
* or user context from ath5k_beacon_config.
|
|
|
*/
|
|
|
static void
|
|
|
-ath5k_beacon_send(struct ath5k_softc *sc)
|
|
|
+ath5k_beacon_send(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ieee80211_vif *vif;
|
|
|
struct ath5k_vif *avf;
|
|
|
struct ath5k_buf *bf;
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
|
|
|
|
|
|
/*
|
|
|
* Check if the previous beacon has gone out. If
|
|
@@ -1862,47 +1849,47 @@ ath5k_beacon_send(struct ath5k_softc *sc)
|
|
|
* indicate a problem and should not occur. If we
|
|
|
* miss too many consecutive beacons reset the device.
|
|
|
*/
|
|
|
- if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
|
|
|
- sc->bmisscount++;
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
|
|
|
- "missed %u consecutive beacons\n", sc->bmisscount);
|
|
|
- if (sc->bmisscount > 10) { /* NB: 10 is a guess */
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
|
|
|
+ ah->bmisscount++;
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
|
|
|
+ "missed %u consecutive beacons\n", ah->bmisscount);
|
|
|
+ if (ah->bmisscount > 10) { /* NB: 10 is a guess */
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
|
|
|
"stuck beacon time (%u missed)\n",
|
|
|
- sc->bmisscount);
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
|
|
|
+ ah->bmisscount);
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
|
|
|
"stuck beacon, resetting\n");
|
|
|
- ieee80211_queue_work(sc->hw, &sc->reset_work);
|
|
|
+ ieee80211_queue_work(ah->hw, &ah->reset_work);
|
|
|
}
|
|
|
return;
|
|
|
}
|
|
|
- if (unlikely(sc->bmisscount != 0)) {
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ if (unlikely(ah->bmisscount != 0)) {
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
|
|
|
"resume beacon xmit after %u misses\n",
|
|
|
- sc->bmisscount);
|
|
|
- sc->bmisscount = 0;
|
|
|
+ ah->bmisscount);
|
|
|
+ ah->bmisscount = 0;
|
|
|
}
|
|
|
|
|
|
- if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
|
|
|
- sc->opmode == NL80211_IFTYPE_MESH_POINT) {
|
|
|
+ if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
|
|
|
+ ah->opmode == NL80211_IFTYPE_MESH_POINT) {
|
|
|
u64 tsf = ath5k_hw_get_tsf64(ah);
|
|
|
u32 tsftu = TSF_TO_TU(tsf);
|
|
|
- int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
|
|
|
- vif = sc->bslot[(slot + 1) % ATH_BCBUF];
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
|
|
|
+ vif = ah->bslot[(slot + 1) % ATH_BCBUF];
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
|
|
|
"tsf %llx tsftu %x intval %u slot %u vif %p\n",
|
|
|
- (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
|
|
|
+ (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
|
|
|
} else /* only one interface */
|
|
|
- vif = sc->bslot[0];
|
|
|
+ vif = ah->bslot[0];
|
|
|
|
|
|
if (!vif)
|
|
|
return;
|
|
|
|
|
|
avf = (void *)vif->drv_priv;
|
|
|
bf = avf->bbuf;
|
|
|
- if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
|
|
|
- sc->opmode == NL80211_IFTYPE_MONITOR)) {
|
|
|
- ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
|
|
|
+ if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
|
|
|
+ ah->opmode == NL80211_IFTYPE_MONITOR)) {
|
|
|
+ ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
|
|
|
return;
|
|
|
}
|
|
|
|
|
@@ -1911,40 +1898,40 @@ ath5k_beacon_send(struct ath5k_softc *sc)
|
|
|
* This should never fail since we check above that no frames
|
|
|
* are still pending on the queue.
|
|
|
*/
|
|
|
- if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
|
|
|
- ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
|
|
|
+ if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
|
|
|
+ ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
|
|
|
/* NB: hw still stops DMA, so proceed */
|
|
|
}
|
|
|
|
|
|
/* refresh the beacon for AP or MESH mode */
|
|
|
- if (sc->opmode == NL80211_IFTYPE_AP ||
|
|
|
- sc->opmode == NL80211_IFTYPE_MESH_POINT)
|
|
|
- ath5k_beacon_update(sc->hw, vif);
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_AP ||
|
|
|
+ ah->opmode == NL80211_IFTYPE_MESH_POINT)
|
|
|
+ ath5k_beacon_update(ah->hw, vif);
|
|
|
|
|
|
- trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
|
|
|
+ trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
|
|
|
|
|
|
- ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
|
|
|
- ath5k_hw_start_tx_dma(ah, sc->bhalq);
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
|
|
|
- sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
|
|
|
+ ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
|
|
|
+ ath5k_hw_start_tx_dma(ah, ah->bhalq);
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
|
|
|
+ ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
|
|
|
|
|
|
- skb = ieee80211_get_buffered_bc(sc->hw, vif);
|
|
|
+ skb = ieee80211_get_buffered_bc(ah->hw, vif);
|
|
|
while (skb) {
|
|
|
- ath5k_tx_queue(sc->hw, skb, sc->cabq);
|
|
|
+ ath5k_tx_queue(ah->hw, skb, ah->cabq);
|
|
|
|
|
|
- if (sc->cabq->txq_len >= sc->cabq->txq_max)
|
|
|
+ if (ah->cabq->txq_len >= ah->cabq->txq_max)
|
|
|
break;
|
|
|
|
|
|
- skb = ieee80211_get_buffered_bc(sc->hw, vif);
|
|
|
+ skb = ieee80211_get_buffered_bc(ah->hw, vif);
|
|
|
}
|
|
|
|
|
|
- sc->bsent++;
|
|
|
+ ah->bsent++;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* ath5k_beacon_update_timers - update beacon timers
|
|
|
*
|
|
|
- * @sc: struct ath5k_softc pointer we are operating on
|
|
|
+ * @ah: struct ath5k_hw pointer we are operating on
|
|
|
* @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
|
|
|
* beacon timer update based on the current HW TSF.
|
|
|
*
|
|
@@ -1958,17 +1945,16 @@ ath5k_beacon_send(struct ath5k_softc *sc)
|
|
|
* function to have it all together in one place.
|
|
|
*/
|
|
|
void
|
|
|
-ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
|
|
|
+ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
u32 nexttbtt, intval, hw_tu, bc_tu;
|
|
|
u64 hw_tsf;
|
|
|
|
|
|
- intval = sc->bintval & AR5K_BEACON_PERIOD;
|
|
|
- if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
|
|
|
+ intval = ah->bintval & AR5K_BEACON_PERIOD;
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
|
|
|
intval /= ATH_BCBUF; /* staggered multi-bss beacons */
|
|
|
if (intval < 15)
|
|
|
- ATH5K_WARN(sc, "intval %u is too low, min 15\n",
|
|
|
+ ATH5K_WARN(ah, "intval %u is too low, min 15\n",
|
|
|
intval);
|
|
|
}
|
|
|
if (WARN_ON(!intval))
|
|
@@ -2007,7 +1993,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
|
|
|
* automatically update the TSF and then we need to reconfigure
|
|
|
* the timers.
|
|
|
*/
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"need to wait for HW TSF sync\n");
|
|
|
return;
|
|
|
} else {
|
|
@@ -2022,7 +2008,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
|
|
|
}
|
|
|
#undef FUDGE
|
|
|
|
|
|
- sc->nexttbtt = nexttbtt;
|
|
|
+ ah->nexttbtt = nexttbtt;
|
|
|
|
|
|
intval |= AR5K_BEACON_ENA;
|
|
|
ath5k_hw_init_beacon(ah, nexttbtt, intval);
|
|
@@ -2032,20 +2018,20 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
|
|
|
* of this function
|
|
|
*/
|
|
|
if (bc_tsf == -1)
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"reconfigured timers based on HW TSF\n");
|
|
|
else if (bc_tsf == 0)
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"reset HW TSF and timers\n");
|
|
|
else
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"updated timers based on beacon TSF\n");
|
|
|
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
|
|
|
"bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
|
|
|
(unsigned long long) bc_tsf,
|
|
|
(unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
|
|
|
- ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
|
|
|
+ ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
|
|
|
intval & AR5K_BEACON_PERIOD,
|
|
|
intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
|
|
|
intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
|
|
@@ -2054,22 +2040,21 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
|
|
|
/**
|
|
|
* ath5k_beacon_config - Configure the beacon queues and interrupts
|
|
|
*
|
|
|
- * @sc: struct ath5k_softc pointer we are operating on
|
|
|
+ * @ah: struct ath5k_hw pointer we are operating on
|
|
|
*
|
|
|
* In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
|
|
|
* interrupts to detect TSF updates only.
|
|
|
*/
|
|
|
void
|
|
|
-ath5k_beacon_config(struct ath5k_softc *sc)
|
|
|
+ath5k_beacon_config(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
unsigned long flags;
|
|
|
|
|
|
- spin_lock_irqsave(&sc->block, flags);
|
|
|
- sc->bmisscount = 0;
|
|
|
- sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
|
|
|
+ spin_lock_irqsave(&ah->block, flags);
|
|
|
+ ah->bmisscount = 0;
|
|
|
+ ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
|
|
|
|
|
|
- if (sc->enable_beacon) {
|
|
|
+ if (ah->enable_beacon) {
|
|
|
/*
|
|
|
* In IBSS mode we use a self-linked tx descriptor and let the
|
|
|
* hardware send the beacons automatically. We have to load it
|
|
@@ -2077,27 +2062,27 @@ ath5k_beacon_config(struct ath5k_softc *sc)
|
|
|
* We use the SWBA interrupt only to keep track of the beacon
|
|
|
* timers in order to detect automatic TSF updates.
|
|
|
*/
|
|
|
- ath5k_beaconq_config(sc);
|
|
|
+ ath5k_beaconq_config(ah);
|
|
|
|
|
|
- sc->imask |= AR5K_INT_SWBA;
|
|
|
+ ah->imask |= AR5K_INT_SWBA;
|
|
|
|
|
|
- if (sc->opmode == NL80211_IFTYPE_ADHOC) {
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_ADHOC) {
|
|
|
if (ath5k_hw_hasveol(ah))
|
|
|
- ath5k_beacon_send(sc);
|
|
|
+ ath5k_beacon_send(ah);
|
|
|
} else
|
|
|
- ath5k_beacon_update_timers(sc, -1);
|
|
|
+ ath5k_beacon_update_timers(ah, -1);
|
|
|
} else {
|
|
|
- ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
|
|
|
+ ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
|
|
|
}
|
|
|
|
|
|
- ath5k_hw_set_imr(ah, sc->imask);
|
|
|
+ ath5k_hw_set_imr(ah, ah->imask);
|
|
|
mmiowb();
|
|
|
- spin_unlock_irqrestore(&sc->block, flags);
|
|
|
+ spin_unlock_irqrestore(&ah->block, flags);
|
|
|
}
|
|
|
|
|
|
static void ath5k_tasklet_beacon(unsigned long data)
|
|
|
{
|
|
|
- struct ath5k_softc *sc = (struct ath5k_softc *) data;
|
|
|
+ struct ath5k_hw *ah = (struct ath5k_hw *) data;
|
|
|
|
|
|
/*
|
|
|
* Software beacon alert--time to send a beacon.
|
|
@@ -2107,20 +2092,20 @@ static void ath5k_tasklet_beacon(unsigned long data)
|
|
|
* transmission time) in order to detect whether
|
|
|
* automatic TSF updates happened.
|
|
|
*/
|
|
|
- if (sc->opmode == NL80211_IFTYPE_ADHOC) {
|
|
|
+ if (ah->opmode == NL80211_IFTYPE_ADHOC) {
|
|
|
/* XXX: only if VEOL supported */
|
|
|
- u64 tsf = ath5k_hw_get_tsf64(sc->ah);
|
|
|
- sc->nexttbtt += sc->bintval;
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
|
|
|
+ u64 tsf = ath5k_hw_get_tsf64(ah);
|
|
|
+ ah->nexttbtt += ah->bintval;
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
|
|
|
"SWBA nexttbtt: %x hw_tu: %x "
|
|
|
"TSF: %llx\n",
|
|
|
- sc->nexttbtt,
|
|
|
+ ah->nexttbtt,
|
|
|
TSF_TO_TU(tsf),
|
|
|
(unsigned long long) tsf);
|
|
|
} else {
|
|
|
- spin_lock(&sc->block);
|
|
|
- ath5k_beacon_send(sc);
|
|
|
- spin_unlock(&sc->block);
|
|
|
+ spin_lock(&ah->block);
|
|
|
+ ath5k_beacon_send(ah);
|
|
|
+ spin_unlock(&ah->block);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -2137,12 +2122,12 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
|
|
|
/* run ANI only when full calibration is not active */
|
|
|
ah->ah_cal_next_ani = jiffies +
|
|
|
msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
|
|
|
- tasklet_schedule(&ah->ah_sc->ani_tasklet);
|
|
|
+ tasklet_schedule(&ah->ani_tasklet);
|
|
|
|
|
|
} else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
|
|
|
ah->ah_cal_next_full = jiffies +
|
|
|
msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
|
|
|
- tasklet_schedule(&ah->ah_sc->calib);
|
|
|
+ tasklet_schedule(&ah->calib);
|
|
|
}
|
|
|
/* we could use SWI to generate enough interrupts to meet our
|
|
|
* calibration interval requirements, if necessary:
|
|
@@ -2150,44 +2135,43 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_schedule_rx(struct ath5k_softc *sc)
|
|
|
+ath5k_schedule_rx(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- sc->rx_pending = true;
|
|
|
- tasklet_schedule(&sc->rxtq);
|
|
|
+ ah->rx_pending = true;
|
|
|
+ tasklet_schedule(&ah->rxtq);
|
|
|
}
|
|
|
|
|
|
static void
|
|
|
-ath5k_schedule_tx(struct ath5k_softc *sc)
|
|
|
+ath5k_schedule_tx(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- sc->tx_pending = true;
|
|
|
- tasklet_schedule(&sc->txtq);
|
|
|
+ ah->tx_pending = true;
|
|
|
+ tasklet_schedule(&ah->txtq);
|
|
|
}
|
|
|
|
|
|
static irqreturn_t
|
|
|
ath5k_intr(int irq, void *dev_id)
|
|
|
{
|
|
|
- struct ath5k_softc *sc = dev_id;
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
+ struct ath5k_hw *ah = dev_id;
|
|
|
enum ath5k_int status;
|
|
|
unsigned int counter = 1000;
|
|
|
|
|
|
- if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
|
|
|
+ if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
|
|
|
((ath5k_get_bus_type(ah) != ATH_AHB) &&
|
|
|
!ath5k_hw_is_intr_pending(ah))))
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
do {
|
|
|
ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
|
|
|
- status, sc->imask);
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
|
|
|
+ status, ah->imask);
|
|
|
if (unlikely(status & AR5K_INT_FATAL)) {
|
|
|
/*
|
|
|
* Fatal errors are unrecoverable.
|
|
|
* Typically these are caused by DMA errors.
|
|
|
*/
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
|
|
|
"fatal int, resetting\n");
|
|
|
- ieee80211_queue_work(sc->hw, &sc->reset_work);
|
|
|
+ ieee80211_queue_work(ah->hw, &ah->reset_work);
|
|
|
} else if (unlikely(status & AR5K_INT_RXORN)) {
|
|
|
/*
|
|
|
* Receive buffers are full. Either the bus is busy or
|
|
@@ -2198,16 +2182,16 @@ ath5k_intr(int irq, void *dev_id)
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* We don't know exactly which versions need a reset -
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* this guess is copied from the HAL.
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*/
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- sc->stats.rxorn_intr++;
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+ ah->stats.rxorn_intr++;
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if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
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- ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
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+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
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"rx overrun, resetting\n");
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- ieee80211_queue_work(sc->hw, &sc->reset_work);
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+ ieee80211_queue_work(ah->hw, &ah->reset_work);
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} else
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- ath5k_schedule_rx(sc);
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+ ath5k_schedule_rx(ah);
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} else {
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if (status & AR5K_INT_SWBA)
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- tasklet_hi_schedule(&sc->beacontq);
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+ tasklet_hi_schedule(&ah->beacontq);
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if (status & AR5K_INT_RXEOL) {
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/*
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@@ -2215,27 +2199,27 @@ ath5k_intr(int irq, void *dev_id)
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* RXE bit is written, but it doesn't work at
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* least on older hardware revs.
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*/
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- sc->stats.rxeol_intr++;
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+ ah->stats.rxeol_intr++;
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}
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if (status & AR5K_INT_TXURN) {
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/* bump tx trigger level */
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ath5k_hw_update_tx_triglevel(ah, true);
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}
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if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
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- ath5k_schedule_rx(sc);
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+ ath5k_schedule_rx(ah);
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if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
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| AR5K_INT_TXERR | AR5K_INT_TXEOL))
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- ath5k_schedule_tx(sc);
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+ ath5k_schedule_tx(ah);
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if (status & AR5K_INT_BMISS) {
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/* TODO */
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}
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if (status & AR5K_INT_MIB) {
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- sc->stats.mib_intr++;
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+ ah->stats.mib_intr++;
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ath5k_hw_update_mib_counters(ah);
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ath5k_ani_mib_intr(ah);
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}
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if (status & AR5K_INT_GPIO)
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- tasklet_schedule(&sc->rf_kill.toggleq);
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+ tasklet_schedule(&ah->rf_kill.toggleq);
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}
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@@ -2244,11 +2228,11 @@ ath5k_intr(int irq, void *dev_id)
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} while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
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- if (sc->rx_pending || sc->tx_pending)
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- ath5k_set_current_imask(sc);
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+ if (ah->rx_pending || ah->tx_pending)
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+ ath5k_set_current_imask(ah);
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if (unlikely(!counter))
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- ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
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+ ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
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ath5k_intr_calibration_poll(ah);
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@@ -2262,28 +2246,27 @@ ath5k_intr(int irq, void *dev_id)
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static void
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ath5k_tasklet_calibrate(unsigned long data)
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{
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- struct ath5k_softc *sc = (void *)data;
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- struct ath5k_hw *ah = sc->ah;
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+ struct ath5k_hw *ah = (void *)data;
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/* Only full calibration for now */
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ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
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- ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
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- ieee80211_frequency_to_channel(sc->curchan->center_freq),
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- sc->curchan->hw_value);
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+ ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
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+ ieee80211_frequency_to_channel(ah->curchan->center_freq),
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+ ah->curchan->hw_value);
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if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
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/*
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* Rfgain is out of bounds, reset the chip
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* to load new gain values.
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*/
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- ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
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- ieee80211_queue_work(sc->hw, &sc->reset_work);
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+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
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+ ieee80211_queue_work(ah->hw, &ah->reset_work);
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}
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- if (ath5k_hw_phy_calibrate(ah, sc->curchan))
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- ATH5K_ERR(sc, "calibration of channel %u failed\n",
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+ if (ath5k_hw_phy_calibrate(ah, ah->curchan))
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+ ATH5K_ERR(ah, "calibration of channel %u failed\n",
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ieee80211_frequency_to_channel(
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- sc->curchan->center_freq));
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+ ah->curchan->center_freq));
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/* Noise floor calibration interrupts rx/tx path while I/Q calibration
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* doesn't.
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@@ -2302,8 +2285,7 @@ ath5k_tasklet_calibrate(unsigned long data)
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static void
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ath5k_tasklet_ani(unsigned long data)
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{
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- struct ath5k_softc *sc = (void *)data;
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- struct ath5k_hw *ah = sc->ah;
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+ struct ath5k_hw *ah = (void *)data;
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ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
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ath5k_ani_calibration(ah);
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@@ -2314,21 +2296,21 @@ ath5k_tasklet_ani(unsigned long data)
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static void
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ath5k_tx_complete_poll_work(struct work_struct *work)
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{
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- struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
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+ struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
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tx_complete_work.work);
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struct ath5k_txq *txq;
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int i;
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bool needreset = false;
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- mutex_lock(&sc->lock);
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+ mutex_lock(&ah->lock);
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- for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
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- if (sc->txqs[i].setup) {
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- txq = &sc->txqs[i];
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+ for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
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+ if (ah->txqs[i].setup) {
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+ txq = &ah->txqs[i];
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spin_lock_bh(&txq->lock);
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if (txq->txq_len > 1) {
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if (txq->txq_poll_mark) {
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- ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
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+ ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
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"TX queue stuck %d\n",
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txq->qnum);
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needreset = true;
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@@ -2344,14 +2326,14 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
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}
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if (needreset) {
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- ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
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+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
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"TX queues stuck, resetting\n");
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- ath5k_reset(sc, NULL, true);
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+ ath5k_reset(ah, NULL, true);
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}
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- mutex_unlock(&sc->lock);
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+ mutex_unlock(&ah->lock);
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- ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
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+ ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
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msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
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}
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@@ -2361,15 +2343,15 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
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\*************************/
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int __devinit
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-ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
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+ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
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{
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- struct ieee80211_hw *hw = sc->hw;
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+ struct ieee80211_hw *hw = ah->hw;
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struct ath_common *common;
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int ret;
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int csz;
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/* Initialize driver private data */
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- SET_IEEE80211_DEV(hw, sc->dev);
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+ SET_IEEE80211_DEV(hw, ah->dev);
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hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
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IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
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IEEE80211_HW_SIGNAL_DBM |
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@@ -2392,39 +2374,29 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
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* Mark the device as detached to avoid processing
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* interrupts until setup is complete.
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*/
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- __set_bit(ATH_STAT_INVALID, sc->status);
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+ __set_bit(ATH_STAT_INVALID, ah->status);
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- sc->opmode = NL80211_IFTYPE_STATION;
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- sc->bintval = 1000;
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- mutex_init(&sc->lock);
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- spin_lock_init(&sc->rxbuflock);
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- spin_lock_init(&sc->txbuflock);
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- spin_lock_init(&sc->block);
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- spin_lock_init(&sc->irqlock);
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+ ah->opmode = NL80211_IFTYPE_STATION;
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+ ah->bintval = 1000;
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+ mutex_init(&ah->lock);
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+ spin_lock_init(&ah->rxbuflock);
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+ spin_lock_init(&ah->txbuflock);
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+ spin_lock_init(&ah->block);
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+ spin_lock_init(&ah->irqlock);
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/* Setup interrupt handler */
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- ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
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+ ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
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if (ret) {
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- ATH5K_ERR(sc, "request_irq failed\n");
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+ ATH5K_ERR(ah, "request_irq failed\n");
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goto err;
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}
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- /* If we passed the test, malloc an ath5k_hw struct */
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- sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
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- if (!sc->ah) {
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- ret = -ENOMEM;
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- ATH5K_ERR(sc, "out of memory\n");
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- goto err_irq;
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- }
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-
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- sc->ah->ah_sc = sc;
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- sc->ah->ah_iobase = sc->iobase;
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- common = ath5k_hw_common(sc->ah);
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+ common = ath5k_hw_common(ah);
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common->ops = &ath5k_common_ops;
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common->bus_ops = bus_ops;
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- common->ah = sc->ah;
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+ common->ah = ah;
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common->hw = hw;
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- common->priv = sc;
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+ common->priv = ah;
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common->clockrate = 40;
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/*
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@@ -2437,12 +2409,12 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
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spin_lock_init(&common->cc_lock);
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/* Initialize device */
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- ret = ath5k_hw_init(sc);
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+ ret = ath5k_hw_init(ah);
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if (ret)
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- goto err_free_ah;
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+ goto err_irq;
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/* set up multi-rate retry capabilities */
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- if (sc->ah->ah_version == AR5K_AR5212) {
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+ if (ah->ah_version == AR5K_AR5212) {
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hw->max_rates = 4;
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hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
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AR5K_INIT_RETRY_LONG);
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@@ -2455,77 +2427,74 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
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if (ret)
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goto err_ah;
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- ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
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- ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
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- sc->ah->ah_mac_srev,
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- sc->ah->ah_phy_revision);
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+ ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
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+ ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
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+ ah->ah_mac_srev,
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+ ah->ah_phy_revision);
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- if (!sc->ah->ah_single_chip) {
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+ if (!ah->ah_single_chip) {
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/* Single chip radio (!RF5111) */
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- if (sc->ah->ah_radio_5ghz_revision &&
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- !sc->ah->ah_radio_2ghz_revision) {
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+ if (ah->ah_radio_5ghz_revision &&
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+ !ah->ah_radio_2ghz_revision) {
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/* No 5GHz support -> report 2GHz radio */
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if (!test_bit(AR5K_MODE_11A,
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- sc->ah->ah_capabilities.cap_mode)) {
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- ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
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+ ah->ah_capabilities.cap_mode)) {
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+ ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
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ath5k_chip_name(AR5K_VERSION_RAD,
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- sc->ah->ah_radio_5ghz_revision),
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- sc->ah->ah_radio_5ghz_revision);
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+ ah->ah_radio_5ghz_revision),
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+ ah->ah_radio_5ghz_revision);
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/* No 2GHz support (5110 and some
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* 5GHz only cards) -> report 5GHz radio */
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} else if (!test_bit(AR5K_MODE_11B,
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- sc->ah->ah_capabilities.cap_mode)) {
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- ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
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+ ah->ah_capabilities.cap_mode)) {
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+ ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
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ath5k_chip_name(AR5K_VERSION_RAD,
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- sc->ah->ah_radio_5ghz_revision),
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- sc->ah->ah_radio_5ghz_revision);
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+ ah->ah_radio_5ghz_revision),
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+ ah->ah_radio_5ghz_revision);
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/* Multiband radio */
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} else {
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- ATH5K_INFO(sc, "RF%s multiband radio found"
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+ ATH5K_INFO(ah, "RF%s multiband radio found"
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" (0x%x)\n",
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ath5k_chip_name(AR5K_VERSION_RAD,
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- sc->ah->ah_radio_5ghz_revision),
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- sc->ah->ah_radio_5ghz_revision);
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+ ah->ah_radio_5ghz_revision),
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+ ah->ah_radio_5ghz_revision);
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}
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}
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/* Multi chip radio (RF5111 - RF2111) ->
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* report both 2GHz/5GHz radios */
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- else if (sc->ah->ah_radio_5ghz_revision &&
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- sc->ah->ah_radio_2ghz_revision) {
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- ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
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+ else if (ah->ah_radio_5ghz_revision &&
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+ ah->ah_radio_2ghz_revision) {
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+ ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
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ath5k_chip_name(AR5K_VERSION_RAD,
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- sc->ah->ah_radio_5ghz_revision),
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- sc->ah->ah_radio_5ghz_revision);
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- ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
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+ ah->ah_radio_5ghz_revision),
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+ ah->ah_radio_5ghz_revision);
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+ ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
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ath5k_chip_name(AR5K_VERSION_RAD,
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- sc->ah->ah_radio_2ghz_revision),
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- sc->ah->ah_radio_2ghz_revision);
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+ ah->ah_radio_2ghz_revision),
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+ ah->ah_radio_2ghz_revision);
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}
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}
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- ath5k_debug_init_device(sc);
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+ ath5k_debug_init_device(ah);
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/* ready to process interrupts */
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- __clear_bit(ATH_STAT_INVALID, sc->status);
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+ __clear_bit(ATH_STAT_INVALID, ah->status);
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return 0;
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err_ah:
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- ath5k_hw_deinit(sc->ah);
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-err_free_ah:
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- kfree(sc->ah);
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+ ath5k_hw_deinit(ah);
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err_irq:
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- free_irq(sc->irq, sc);
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+ free_irq(ah->irq, ah);
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err:
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return ret;
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}
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static int
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-ath5k_stop_locked(struct ath5k_softc *sc)
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+ath5k_stop_locked(struct ath5k_hw *ah)
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{
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- struct ath5k_hw *ah = sc->ah;
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|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
|
|
|
- test_bit(ATH_STAT_INVALID, sc->status));
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
|
|
|
+ test_bit(ATH_STAT_INVALID, ah->status));
|
|
|
|
|
|
/*
|
|
|
* Shutdown the hardware and driver:
|
|
@@ -2542,15 +2511,15 @@ ath5k_stop_locked(struct ath5k_softc *sc)
|
|
|
* Note that some of this work is not possible if the
|
|
|
* hardware is gone (invalid).
|
|
|
*/
|
|
|
- ieee80211_stop_queues(sc->hw);
|
|
|
+ ieee80211_stop_queues(ah->hw);
|
|
|
|
|
|
- if (!test_bit(ATH_STAT_INVALID, sc->status)) {
|
|
|
- ath5k_led_off(sc);
|
|
|
+ if (!test_bit(ATH_STAT_INVALID, ah->status)) {
|
|
|
+ ath5k_led_off(ah);
|
|
|
ath5k_hw_set_imr(ah, 0);
|
|
|
- synchronize_irq(sc->irq);
|
|
|
- ath5k_rx_stop(sc);
|
|
|
+ synchronize_irq(ah->irq);
|
|
|
+ ath5k_rx_stop(ah);
|
|
|
ath5k_hw_dma_stop(ah);
|
|
|
- ath5k_drain_tx_buffs(sc);
|
|
|
+ ath5k_drain_tx_buffs(ah);
|
|
|
ath5k_hw_phy_disable(ah);
|
|
|
}
|
|
|
|
|
@@ -2558,21 +2527,20 @@ ath5k_stop_locked(struct ath5k_softc *sc)
|
|
|
}
|
|
|
|
|
|
int
|
|
|
-ath5k_init_hw(struct ath5k_softc *sc)
|
|
|
+ath5k_init_hw(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
int ret, i;
|
|
|
|
|
|
- mutex_lock(&sc->lock);
|
|
|
+ mutex_lock(&ah->lock);
|
|
|
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
|
|
|
|
|
|
/*
|
|
|
* Stop anything previously setup. This is safe
|
|
|
* no matter this is the first time through or not.
|
|
|
*/
|
|
|
- ath5k_stop_locked(sc);
|
|
|
+ ath5k_stop_locked(ah);
|
|
|
|
|
|
/*
|
|
|
* The basic interface to setting the hardware in a good
|
|
@@ -2581,12 +2549,12 @@ ath5k_init_hw(struct ath5k_softc *sc)
|
|
|
* be followed by initialization of the appropriate bits
|
|
|
* and then setup of the interrupt mask.
|
|
|
*/
|
|
|
- sc->curchan = sc->hw->conf.channel;
|
|
|
- sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
|
|
|
+ ah->curchan = ah->hw->conf.channel;
|
|
|
+ ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
|
|
|
AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
|
|
|
AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
|
|
|
|
|
|
- ret = ath5k_reset(sc, NULL, false);
|
|
|
+ ret = ath5k_reset(ah, NULL, false);
|
|
|
if (ret)
|
|
|
goto done;
|
|
|
|
|
@@ -2603,29 +2571,29 @@ ath5k_init_hw(struct ath5k_softc *sc)
|
|
|
* rate */
|
|
|
ah->ah_ack_bitrate_high = true;
|
|
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
|
|
|
- sc->bslot[i] = NULL;
|
|
|
+ for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
|
|
|
+ ah->bslot[i] = NULL;
|
|
|
|
|
|
ret = 0;
|
|
|
done:
|
|
|
mmiowb();
|
|
|
- mutex_unlock(&sc->lock);
|
|
|
+ mutex_unlock(&ah->lock);
|
|
|
|
|
|
- ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
|
|
|
+ ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
|
|
|
msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
|
|
|
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-static void ath5k_stop_tasklets(struct ath5k_softc *sc)
|
|
|
+static void ath5k_stop_tasklets(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- sc->rx_pending = false;
|
|
|
- sc->tx_pending = false;
|
|
|
- tasklet_kill(&sc->rxtq);
|
|
|
- tasklet_kill(&sc->txtq);
|
|
|
- tasklet_kill(&sc->calib);
|
|
|
- tasklet_kill(&sc->beacontq);
|
|
|
- tasklet_kill(&sc->ani_tasklet);
|
|
|
+ ah->rx_pending = false;
|
|
|
+ ah->tx_pending = false;
|
|
|
+ tasklet_kill(&ah->rxtq);
|
|
|
+ tasklet_kill(&ah->txtq);
|
|
|
+ tasklet_kill(&ah->calib);
|
|
|
+ tasklet_kill(&ah->beacontq);
|
|
|
+ tasklet_kill(&ah->ani_tasklet);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2635,13 +2603,13 @@ static void ath5k_stop_tasklets(struct ath5k_softc *sc)
|
|
|
* stop is preempted).
|
|
|
*/
|
|
|
int
|
|
|
-ath5k_stop_hw(struct ath5k_softc *sc)
|
|
|
+ath5k_stop_hw(struct ath5k_hw *ah)
|
|
|
{
|
|
|
int ret;
|
|
|
|
|
|
- mutex_lock(&sc->lock);
|
|
|
- ret = ath5k_stop_locked(sc);
|
|
|
- if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
|
|
|
+ mutex_lock(&ah->lock);
|
|
|
+ ret = ath5k_stop_locked(ah);
|
|
|
+ if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
|
|
|
/*
|
|
|
* Don't set the card in full sleep mode!
|
|
|
*
|
|
@@ -2662,20 +2630,20 @@ ath5k_stop_hw(struct ath5k_softc *sc)
|
|
|
* and Sam's HAL do anyway). Instead Perform a full reset
|
|
|
* on the device (same as initial state after attach) and
|
|
|
* leave it idle (keep MAC/BB on warm reset) */
|
|
|
- ret = ath5k_hw_on_hold(sc->ah);
|
|
|
+ ret = ath5k_hw_on_hold(ah);
|
|
|
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
|
|
|
"putting device to sleep\n");
|
|
|
}
|
|
|
|
|
|
mmiowb();
|
|
|
- mutex_unlock(&sc->lock);
|
|
|
+ mutex_unlock(&ah->lock);
|
|
|
|
|
|
- ath5k_stop_tasklets(sc);
|
|
|
+ ath5k_stop_tasklets(ah);
|
|
|
|
|
|
- cancel_delayed_work_sync(&sc->tx_complete_work);
|
|
|
+ cancel_delayed_work_sync(&ah->tx_complete_work);
|
|
|
|
|
|
- ath5k_rfkill_hw_stop(sc->ah);
|
|
|
+ ath5k_rfkill_hw_stop(ah);
|
|
|
|
|
|
return ret;
|
|
|
}
|
|
@@ -2684,47 +2652,46 @@ ath5k_stop_hw(struct ath5k_softc *sc)
|
|
|
* Reset the hardware. If chan is not NULL, then also pause rx/tx
|
|
|
* and change to the given channel.
|
|
|
*
|
|
|
- * This should be called with sc->lock.
|
|
|
+ * This should be called with ah->lock.
|
|
|
*/
|
|
|
static int
|
|
|
-ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
|
|
|
+ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
|
|
|
bool skip_pcu)
|
|
|
{
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
|
int ret, ani_mode;
|
|
|
bool fast;
|
|
|
|
|
|
- ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
|
|
|
+ ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
|
|
|
|
|
|
ath5k_hw_set_imr(ah, 0);
|
|
|
- synchronize_irq(sc->irq);
|
|
|
- ath5k_stop_tasklets(sc);
|
|
|
+ synchronize_irq(ah->irq);
|
|
|
+ ath5k_stop_tasklets(ah);
|
|
|
|
|
|
/* Save ani mode and disable ANI during
|
|
|
* reset. If we don't we might get false
|
|
|
* PHY error interrupts. */
|
|
|
- ani_mode = ah->ah_sc->ani_state.ani_mode;
|
|
|
+ ani_mode = ah->ani_state.ani_mode;
|
|
|
ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
|
|
|
|
|
|
/* We are going to empty hw queues
|
|
|
* so we should also free any remaining
|
|
|
* tx buffers */
|
|
|
- ath5k_drain_tx_buffs(sc);
|
|
|
+ ath5k_drain_tx_buffs(ah);
|
|
|
if (chan)
|
|
|
- sc->curchan = chan;
|
|
|
+ ah->curchan = chan;
|
|
|
|
|
|
fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
|
|
|
|
|
|
- ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, skip_pcu);
|
|
|
+ ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
|
|
|
+ ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
|
|
|
goto err;
|
|
|
}
|
|
|
|
|
|
- ret = ath5k_rx_start(sc);
|
|
|
+ ret = ath5k_rx_start(ah);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "can't start recv logic\n");
|
|
|
+ ATH5K_ERR(ah, "can't start recv logic\n");
|
|
|
goto err;
|
|
|
}
|
|
|
|
|
@@ -2736,7 +2703,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
|
|
|
ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
|
|
|
|
|
|
/* clear survey data and cycle counters */
|
|
|
- memset(&sc->survey, 0, sizeof(sc->survey));
|
|
|
+ memset(&ah->survey, 0, sizeof(ah->survey));
|
|
|
spin_lock_bh(&common->cc_lock);
|
|
|
ath_hw_cycle_counters_update(common);
|
|
|
memset(&common->cc_survey, 0, sizeof(common->cc_survey));
|
|
@@ -2752,12 +2719,12 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
|
|
|
*
|
|
|
* XXX needed?
|
|
|
*/
|
|
|
-/* ath5k_chan_change(sc, c); */
|
|
|
+/* ath5k_chan_change(ah, c); */
|
|
|
|
|
|
- ath5k_beacon_config(sc);
|
|
|
+ ath5k_beacon_config(ah);
|
|
|
/* intrs are enabled by ath5k_beacon_config */
|
|
|
|
|
|
- ieee80211_wake_queues(sc->hw);
|
|
|
+ ieee80211_wake_queues(ah->hw);
|
|
|
|
|
|
return 0;
|
|
|
err:
|
|
@@ -2766,20 +2733,19 @@ err:
|
|
|
|
|
|
static void ath5k_reset_work(struct work_struct *work)
|
|
|
{
|
|
|
- struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
|
|
|
+ struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
|
|
|
reset_work);
|
|
|
|
|
|
- mutex_lock(&sc->lock);
|
|
|
- ath5k_reset(sc, NULL, true);
|
|
|
- mutex_unlock(&sc->lock);
|
|
|
+ mutex_lock(&ah->lock);
|
|
|
+ ath5k_reset(ah, NULL, true);
|
|
|
+ mutex_unlock(&ah->lock);
|
|
|
}
|
|
|
|
|
|
static int __devinit
|
|
|
ath5k_init(struct ieee80211_hw *hw)
|
|
|
{
|
|
|
|
|
|
- struct ath5k_softc *sc = hw->priv;
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
+ struct ath5k_hw *ah = hw->priv;
|
|
|
struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
|
|
|
struct ath5k_txq *txq;
|
|
|
u8 mac[ETH_ALEN] = {};
|
|
@@ -2798,7 +2764,7 @@ ath5k_init(struct ieee80211_hw *hw)
|
|
|
if (ret < 0)
|
|
|
goto err;
|
|
|
if (ret > 0)
|
|
|
- __set_bit(ATH_STAT_MRRETRY, sc->status);
|
|
|
+ __set_bit(ATH_STAT_MRRETRY, ah->status);
|
|
|
|
|
|
/*
|
|
|
* Collect the channel list. The 802.11 layer
|
|
@@ -2808,16 +2774,16 @@ ath5k_init(struct ieee80211_hw *hw)
|
|
|
*/
|
|
|
ret = ath5k_setup_bands(hw);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "can't get channels\n");
|
|
|
+ ATH5K_ERR(ah, "can't get channels\n");
|
|
|
goto err;
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
* Allocate tx+rx descriptors and populate the lists.
|
|
|
*/
|
|
|
- ret = ath5k_desc_alloc(sc);
|
|
|
+ ret = ath5k_desc_alloc(ah);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "can't allocate descriptors\n");
|
|
|
+ ATH5K_ERR(ah, "can't allocate descriptors\n");
|
|
|
goto err;
|
|
|
}
|
|
|
|
|
@@ -2829,14 +2795,14 @@ ath5k_init(struct ieee80211_hw *hw)
|
|
|
*/
|
|
|
ret = ath5k_beaconq_setup(ah);
|
|
|
if (ret < 0) {
|
|
|
- ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
|
|
|
+ ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
|
|
|
goto err_desc;
|
|
|
}
|
|
|
- sc->bhalq = ret;
|
|
|
- sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
|
|
|
- if (IS_ERR(sc->cabq)) {
|
|
|
- ATH5K_ERR(sc, "can't setup cab queue\n");
|
|
|
- ret = PTR_ERR(sc->cabq);
|
|
|
+ ah->bhalq = ret;
|
|
|
+ ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
|
|
|
+ if (IS_ERR(ah->cabq)) {
|
|
|
+ ATH5K_ERR(ah, "can't setup cab queue\n");
|
|
|
+ ret = PTR_ERR(ah->cabq);
|
|
|
goto err_bhal;
|
|
|
}
|
|
|
|
|
@@ -2845,97 +2811,97 @@ ath5k_init(struct ieee80211_hw *hw)
|
|
|
if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
|
|
|
/* This order matches mac80211's queue priority, so we can
|
|
|
* directly use the mac80211 queue number without any mapping */
|
|
|
- txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
|
|
|
+ txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
|
|
|
if (IS_ERR(txq)) {
|
|
|
- ATH5K_ERR(sc, "can't setup xmit queue\n");
|
|
|
+ ATH5K_ERR(ah, "can't setup xmit queue\n");
|
|
|
ret = PTR_ERR(txq);
|
|
|
goto err_queues;
|
|
|
}
|
|
|
- txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
|
|
|
+ txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
|
|
|
if (IS_ERR(txq)) {
|
|
|
- ATH5K_ERR(sc, "can't setup xmit queue\n");
|
|
|
+ ATH5K_ERR(ah, "can't setup xmit queue\n");
|
|
|
ret = PTR_ERR(txq);
|
|
|
goto err_queues;
|
|
|
}
|
|
|
- txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
|
|
|
+ txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
|
|
|
if (IS_ERR(txq)) {
|
|
|
- ATH5K_ERR(sc, "can't setup xmit queue\n");
|
|
|
+ ATH5K_ERR(ah, "can't setup xmit queue\n");
|
|
|
ret = PTR_ERR(txq);
|
|
|
goto err_queues;
|
|
|
}
|
|
|
- txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
|
|
|
+ txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
|
|
|
if (IS_ERR(txq)) {
|
|
|
- ATH5K_ERR(sc, "can't setup xmit queue\n");
|
|
|
+ ATH5K_ERR(ah, "can't setup xmit queue\n");
|
|
|
ret = PTR_ERR(txq);
|
|
|
goto err_queues;
|
|
|
}
|
|
|
hw->queues = 4;
|
|
|
} else {
|
|
|
/* older hardware (5210) can only support one data queue */
|
|
|
- txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
|
|
|
+ txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
|
|
|
if (IS_ERR(txq)) {
|
|
|
- ATH5K_ERR(sc, "can't setup xmit queue\n");
|
|
|
+ ATH5K_ERR(ah, "can't setup xmit queue\n");
|
|
|
ret = PTR_ERR(txq);
|
|
|
goto err_queues;
|
|
|
}
|
|
|
hw->queues = 1;
|
|
|
}
|
|
|
|
|
|
- tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
|
|
|
- tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
|
|
|
- tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
|
|
|
- tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
|
|
|
- tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
|
|
|
+ tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
|
|
|
+ tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
|
|
|
+ tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
|
|
|
+ tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
|
|
|
+ tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
|
|
|
|
|
|
- INIT_WORK(&sc->reset_work, ath5k_reset_work);
|
|
|
- INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
|
|
|
+ INIT_WORK(&ah->reset_work, ath5k_reset_work);
|
|
|
+ INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
|
|
|
|
|
|
ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "unable to read address from EEPROM\n");
|
|
|
+ ATH5K_ERR(ah, "unable to read address from EEPROM\n");
|
|
|
goto err_queues;
|
|
|
}
|
|
|
|
|
|
SET_IEEE80211_PERM_ADDR(hw, mac);
|
|
|
- memcpy(&sc->lladdr, mac, ETH_ALEN);
|
|
|
+ memcpy(&ah->lladdr, mac, ETH_ALEN);
|
|
|
/* All MAC address bits matter for ACKs */
|
|
|
- ath5k_update_bssid_mask_and_opmode(sc, NULL);
|
|
|
+ ath5k_update_bssid_mask_and_opmode(ah, NULL);
|
|
|
|
|
|
regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
|
|
|
ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "can't initialize regulatory system\n");
|
|
|
+ ATH5K_ERR(ah, "can't initialize regulatory system\n");
|
|
|
goto err_queues;
|
|
|
}
|
|
|
|
|
|
ret = ieee80211_register_hw(hw);
|
|
|
if (ret) {
|
|
|
- ATH5K_ERR(sc, "can't register ieee80211 hw\n");
|
|
|
+ ATH5K_ERR(ah, "can't register ieee80211 hw\n");
|
|
|
goto err_queues;
|
|
|
}
|
|
|
|
|
|
if (!ath_is_world_regd(regulatory))
|
|
|
regulatory_hint(hw->wiphy, regulatory->alpha2);
|
|
|
|
|
|
- ath5k_init_leds(sc);
|
|
|
+ ath5k_init_leds(ah);
|
|
|
|
|
|
- ath5k_sysfs_register(sc);
|
|
|
+ ath5k_sysfs_register(ah);
|
|
|
|
|
|
return 0;
|
|
|
err_queues:
|
|
|
- ath5k_txq_release(sc);
|
|
|
+ ath5k_txq_release(ah);
|
|
|
err_bhal:
|
|
|
- ath5k_hw_release_tx_queue(ah, sc->bhalq);
|
|
|
+ ath5k_hw_release_tx_queue(ah, ah->bhalq);
|
|
|
err_desc:
|
|
|
- ath5k_desc_free(sc);
|
|
|
+ ath5k_desc_free(ah);
|
|
|
err:
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
void
|
|
|
-ath5k_deinit_softc(struct ath5k_softc *sc)
|
|
|
+ath5k_deinit_softc(struct ath5k_hw *ah)
|
|
|
{
|
|
|
- struct ieee80211_hw *hw = sc->hw;
|
|
|
+ struct ieee80211_hw *hw = ah->hw;
|
|
|
|
|
|
/*
|
|
|
* NB: the order of these is important:
|
|
@@ -2951,24 +2917,23 @@ ath5k_deinit_softc(struct ath5k_softc *sc)
|
|
|
* Other than that, it's straightforward...
|
|
|
*/
|
|
|
ieee80211_unregister_hw(hw);
|
|
|
- ath5k_desc_free(sc);
|
|
|
- ath5k_txq_release(sc);
|
|
|
- ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
|
|
|
- ath5k_unregister_leds(sc);
|
|
|
+ ath5k_desc_free(ah);
|
|
|
+ ath5k_txq_release(ah);
|
|
|
+ ath5k_hw_release_tx_queue(ah, ah->bhalq);
|
|
|
+ ath5k_unregister_leds(ah);
|
|
|
|
|
|
- ath5k_sysfs_unregister(sc);
|
|
|
+ ath5k_sysfs_unregister(ah);
|
|
|
/*
|
|
|
* NB: can't reclaim these until after ieee80211_ifdetach
|
|
|
* returns because we'll get called back to reclaim node
|
|
|
* state and potentially want to use them.
|
|
|
*/
|
|
|
- ath5k_hw_deinit(sc->ah);
|
|
|
- kfree(sc->ah);
|
|
|
- free_irq(sc->irq, sc);
|
|
|
+ ath5k_hw_deinit(ah);
|
|
|
+ free_irq(ah->irq, ah);
|
|
|
}
|
|
|
|
|
|
bool
|
|
|
-ath5k_any_vif_assoc(struct ath5k_softc *sc)
|
|
|
+ath5k_any_vif_assoc(struct ath5k_hw *ah)
|
|
|
{
|
|
|
struct ath5k_vif_iter_data iter_data;
|
|
|
iter_data.hw_macaddr = NULL;
|
|
@@ -2976,7 +2941,7 @@ ath5k_any_vif_assoc(struct ath5k_softc *sc)
|
|
|
iter_data.need_set_hw_addr = false;
|
|
|
iter_data.found_active = true;
|
|
|
|
|
|
- ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
|
|
|
+ ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
|
|
|
&iter_data);
|
|
|
return iter_data.any_assoc;
|
|
|
}
|
|
@@ -2984,8 +2949,7 @@ ath5k_any_vif_assoc(struct ath5k_softc *sc)
|
|
|
void
|
|
|
ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
|
|
|
{
|
|
|
- struct ath5k_softc *sc = hw->priv;
|
|
|
- struct ath5k_hw *ah = sc->ah;
|
|
|
+ struct ath5k_hw *ah = hw->priv;
|
|
|
u32 rfilt;
|
|
|
rfilt = ath5k_hw_get_rx_filter(ah);
|
|
|
if (enable)
|
|
@@ -2993,5 +2957,5 @@ ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
|
|
|
else
|
|
|
rfilt &= ~AR5K_RX_FILTER_BEACON;
|
|
|
ath5k_hw_set_rx_filter(ah, rfilt);
|
|
|
- sc->filter_flags = rfilt;
|
|
|
+ ah->filter_flags = rfilt;
|
|
|
}
|