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@@ -26,8 +26,12 @@
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#define SUPPORTED_FW_RELEASE 0
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#define SUPPORTED_FW_RELEASE 0
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#define SUPPORTED_FW_BUILD 636
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#define SUPPORTED_FW_BUILD 636
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+/* QCA988X 1.0 definitions (unsupported) */
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+#define QCA988X_HW_1_0_CHIP_ID_REV 0x0
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+
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/* QCA988X 2.0 definitions */
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/* QCA988X 2.0 definitions */
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#define QCA988X_HW_2_0_VERSION 0x4100016c
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#define QCA988X_HW_2_0_VERSION 0x4100016c
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+#define QCA988X_HW_2_0_CHIP_ID_REV 0x2
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#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0"
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#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0"
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#define QCA988X_HW_2_0_FW_FILE "firmware.bin"
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#define QCA988X_HW_2_0_FW_FILE "firmware.bin"
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#define QCA988X_HW_2_0_OTP_FILE "otp.bin"
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#define QCA988X_HW_2_0_OTP_FILE "otp.bin"
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@@ -164,6 +168,10 @@ enum ath10k_mcast2ucast_mode {
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#define SOC_LPO_CAL_ENABLE_LSB 20
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#define SOC_LPO_CAL_ENABLE_LSB 20
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#define SOC_LPO_CAL_ENABLE_MASK 0x00100000
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#define SOC_LPO_CAL_ENABLE_MASK 0x00100000
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+#define SOC_CHIP_ID_ADDRESS 0x000000ec
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+#define SOC_CHIP_ID_REV_LSB 8
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+#define SOC_CHIP_ID_REV_MASK 0x00000f00
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+
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#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
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#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
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#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
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#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
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#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
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#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
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