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clocksource: cadence_ttc_timer: Switch to sched_clock_register()

The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.

Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
Cc: Michal Simek <monstr@monstr.eu>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Stephen Boyd 11 years ago
parent
commit
dfded00902
1 changed files with 2 additions and 2 deletions
  1. 2 2
      drivers/clocksource/cadence_ttc_timer.c

+ 2 - 2
drivers/clocksource/cadence_ttc_timer.c

@@ -158,7 +158,7 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
 				TTC_COUNT_VAL_OFFSET);
 				TTC_COUNT_VAL_OFFSET);
 }
 }
 
 
-static u32 notrace ttc_sched_clock_read(void)
+static u64 notrace ttc_sched_clock_read(void)
 {
 {
 	return __raw_readl(ttc_sched_clock_val_reg);
 	return __raw_readl(ttc_sched_clock_val_reg);
 }
 }
@@ -306,7 +306,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
 	}
 	}
 
 
 	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
 	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
-	setup_sched_clock(ttc_sched_clock_read, 16,
+	sched_clock_register(ttc_sched_clock_read, 16,
 			clk_get_rate(ttccs->ttc.clk) / PRESCALE);
 			clk_get_rate(ttccs->ttc.clk) / PRESCALE);
 }
 }