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drm/i915: Parametrize CBR_DPLLBMD_PIPE defines

Apply a bit of polish by parametrizing the CBR_DPLLBMD_PIPE defines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170913140900.6972-3-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Ville Syrjälä 8 years ago
parent
ecf837d98e
commit
dfa311f0d8
2 changed files with 2 additions and 3 deletions
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  1. 1 2
      drivers/gpu/drm/i915/i915_reg.h
  2. 1 1
      drivers/gpu/drm/i915/intel_display.c

+ 1 - 2
drivers/gpu/drm/i915/i915_reg.h
View File 

@@ -5684,8 +5684,7 @@ enum {
 
 #define  CBR_PWM_CLOCK_MUX_SELECT	(1<<30)
 
 
 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
 
-#define  CBR_DPLLBMD_PIPE_C		(1<<29)
 
-#define  CBR_DPLLBMD_PIPE_B		(1<<18)
 
+#define  CBR_DPLLBMD_PIPE(pipe)		(1<<(7+(pipe)*11)) /* pipes B and C */
 
 
 /* FIFO watermark sizes etc */
 
 #define G4X_FIFO_LINE_SIZE	64

+ 1 - 1
drivers/gpu/drm/i915/intel_display.c
View File 

@@ -1539,7 +1539,7 @@ static void chv_enable_pll(struct intel_crtc *crtc,
 
 		 * DPLLCMD is AWOL. Use chicken bits to propagate
 
 		 * the value from DPLLBMD to either pipe B or C.
 
 		 */
 
-		I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
 
+		I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
 
 		I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
 
 		I915_WRITE(CBR4_VLV, 0);
 
 		dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;