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@@ -69,7 +69,12 @@ static const char * const smca_umc_block_names[] = {
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"misc_umc"
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};
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-struct smca_bank_name smca_bank_names[] = {
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+struct smca_bank_name {
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+ const char *name; /* Short name for sysfs */
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+ const char *long_name; /* Long name for pretty-printing */
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+};
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+
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+static struct smca_bank_name smca_names[] = {
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[SMCA_LS] = { "load_store", "Load Store Unit" },
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[SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" },
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[SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" },
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@@ -84,9 +89,25 @@ struct smca_bank_name smca_bank_names[] = {
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[SMCA_PSP] = { "psp", "Platform Security Processor" },
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[SMCA_SMU] = { "smu", "System Management Unit" },
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};
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-EXPORT_SYMBOL_GPL(smca_bank_names);
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-static struct smca_hwid_mcatype smca_hwid_mcatypes[] = {
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+const char *smca_get_name(enum smca_bank_types t)
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+{
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+ if (t >= N_SMCA_BANK_TYPES)
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+ return NULL;
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+
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+ return smca_names[t].name;
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+}
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+
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+const char *smca_get_long_name(enum smca_bank_types t)
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+{
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+ if (t >= N_SMCA_BANK_TYPES)
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+ return NULL;
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+
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+ return smca_names[t].long_name;
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+}
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+EXPORT_SYMBOL_GPL(smca_get_long_name);
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+
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+static struct smca_hwid smca_hwid_mcatypes[] = {
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/* { bank_type, hwid_mcatype, xec_bitmap } */
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/* ZN Core (HWID=0xB0) MCA types */
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@@ -116,7 +137,7 @@ static struct smca_hwid_mcatype smca_hwid_mcatypes[] = {
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{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 },
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};
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-struct smca_bank_info smca_banks[MAX_NR_BANKS];
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+struct smca_bank smca_banks[MAX_NR_BANKS];
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EXPORT_SYMBOL_GPL(smca_banks);
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/*
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@@ -142,35 +163,34 @@ static void default_deferred_error_interrupt(void)
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}
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void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
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-/*
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- * CPU Initialization
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- */
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-
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static void get_smca_bank_info(unsigned int bank)
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{
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unsigned int i, hwid_mcatype, cpu = smp_processor_id();
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- struct smca_hwid_mcatype *type;
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- u32 high, instanceId;
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- u16 hwid, mcatype;
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+ struct smca_hwid *s_hwid;
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+ u32 high, instance_id;
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/* Collect bank_info using CPU 0 for now. */
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if (cpu)
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return;
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- if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instanceId, &high)) {
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+ if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instance_id, &high)) {
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pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
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return;
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}
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- hwid = high & MCI_IPID_HWID;
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- mcatype = (high & MCI_IPID_MCATYPE) >> 16;
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- hwid_mcatype = HWID_MCATYPE(hwid, mcatype);
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+ hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
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+ (high & MCI_IPID_MCATYPE) >> 16);
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for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
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- type = &smca_hwid_mcatypes[i];
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- if (hwid_mcatype == type->hwid_mcatype) {
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- smca_banks[bank].type = type;
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- smca_banks[bank].type_instance = instanceId;
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+ s_hwid = &smca_hwid_mcatypes[i];
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+ if (hwid_mcatype == s_hwid->hwid_mcatype) {
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+
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+ WARN(smca_banks[bank].hwid,
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+ "Bank %s already initialized!\n",
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+ smca_get_name(s_hwid->bank_type));
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+
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+ smca_banks[bank].hwid = s_hwid;
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+ smca_banks[bank].id = instance_id;
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break;
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}
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}
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@@ -533,6 +553,206 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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deferred_error_interrupt_enable(c);
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}
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+int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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+{
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+ u64 dram_base_addr, dram_limit_addr, dram_hole_base;
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+ /* We start from the normalized address */
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+ u64 ret_addr = norm_addr;
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+
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+ u32 tmp;
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+
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+ u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
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+ u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
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+ u8 intlv_addr_sel, intlv_addr_bit;
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+ u8 num_intlv_bits, hashed_bit;
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+ u8 lgcy_mmio_hole_en, base = 0;
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+ u8 cs_mask, cs_id = 0;
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+ bool hash_enabled = false;
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+
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+ /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
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+ if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
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+ goto out_err;
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+
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+ /* Remove HiAddrOffset from normalized address, if enabled: */
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+ if (tmp & BIT(0)) {
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+ u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
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+
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+ if (norm_addr >= hi_addr_offset) {
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+ ret_addr -= hi_addr_offset;
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+ base = 1;
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+ }
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+ }
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+
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+ /* Read D18F0x110 (DramBaseAddress). */
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+ if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
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+ goto out_err;
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+
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+ /* Check if address range is valid. */
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+ if (!(tmp & BIT(0))) {
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+ pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
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+ __func__, tmp);
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+ goto out_err;
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+ }
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+
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+ lgcy_mmio_hole_en = tmp & BIT(1);
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+ intlv_num_chan = (tmp >> 4) & 0xF;
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+ intlv_addr_sel = (tmp >> 8) & 0x7;
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+ dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16;
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+
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+ /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
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+ if (intlv_addr_sel > 3) {
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+ pr_err("%s: Invalid interleave address select %d.\n",
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+ __func__, intlv_addr_sel);
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+ goto out_err;
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+ }
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+
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+ /* Read D18F0x114 (DramLimitAddress). */
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+ if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
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+ goto out_err;
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+
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+ intlv_num_sockets = (tmp >> 8) & 0x1;
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+ intlv_num_dies = (tmp >> 10) & 0x3;
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+ dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
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+
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+ intlv_addr_bit = intlv_addr_sel + 8;
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+
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+ /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
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+ switch (intlv_num_chan) {
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+ case 0: intlv_num_chan = 0; break;
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+ case 1: intlv_num_chan = 1; break;
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+ case 3: intlv_num_chan = 2; break;
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+ case 5: intlv_num_chan = 3; break;
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+ case 7: intlv_num_chan = 4; break;
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+
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+ case 8: intlv_num_chan = 1;
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+ hash_enabled = true;
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+ break;
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+ default:
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+ pr_err("%s: Invalid number of interleaved channels %d.\n",
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+ __func__, intlv_num_chan);
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+ goto out_err;
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+ }
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+
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+ num_intlv_bits = intlv_num_chan;
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+
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+ if (intlv_num_dies > 2) {
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+ pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
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+ __func__, intlv_num_dies);
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+ goto out_err;
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+ }
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+
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+ num_intlv_bits += intlv_num_dies;
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+
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+ /* Add a bit if sockets are interleaved. */
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+ num_intlv_bits += intlv_num_sockets;
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+
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+ /* Assert num_intlv_bits <= 4 */
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+ if (num_intlv_bits > 4) {
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+ pr_err("%s: Invalid interleave bits %d.\n",
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+ __func__, num_intlv_bits);
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+ goto out_err;
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+ }
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+
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+ if (num_intlv_bits > 0) {
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+ u64 temp_addr_x, temp_addr_i, temp_addr_y;
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+ u8 die_id_bit, sock_id_bit, cs_fabric_id;
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+
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+ /*
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+ * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
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+ * This is the fabric id for this coherent slave. Use
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+ * umc/channel# as instance id of the coherent slave
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+ * for FICAA.
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+ */
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+ if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
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+ goto out_err;
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+
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+ cs_fabric_id = (tmp >> 8) & 0xFF;
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+ die_id_bit = 0;
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+
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+ /* If interleaved over more than 1 channel: */
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+ if (intlv_num_chan) {
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+ die_id_bit = intlv_num_chan;
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+ cs_mask = (1 << die_id_bit) - 1;
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+ cs_id = cs_fabric_id & cs_mask;
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+ }
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+
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+ sock_id_bit = die_id_bit;
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+
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+ /* Read D18F1x208 (SystemFabricIdMask). */
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+ if (intlv_num_dies || intlv_num_sockets)
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+ if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
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+ goto out_err;
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+
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+ /* If interleaved over more than 1 die. */
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+ if (intlv_num_dies) {
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+ sock_id_bit = die_id_bit + intlv_num_dies;
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+ die_id_shift = (tmp >> 24) & 0xF;
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+ die_id_mask = (tmp >> 8) & 0xFF;
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+
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+ cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
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+ }
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+
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+ /* If interleaved over more than 1 socket. */
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+ if (intlv_num_sockets) {
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+ socket_id_shift = (tmp >> 28) & 0xF;
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+ socket_id_mask = (tmp >> 16) & 0xFF;
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+
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+ cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
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+ }
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+
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+ /*
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+ * The pre-interleaved address consists of XXXXXXIIIYYYYY
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+ * where III is the ID for this CS, and XXXXXXYYYYY are the
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+ * address bits from the post-interleaved address.
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+ * "num_intlv_bits" has been calculated to tell us how many "I"
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+ * bits there are. "intlv_addr_bit" tells us how many "Y" bits
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+ * there are (where "I" starts).
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+ */
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+ temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
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+ temp_addr_i = (cs_id << intlv_addr_bit);
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+ temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
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+ ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
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+ }
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+
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+ /* Add dram base address */
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+ ret_addr += dram_base_addr;
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+
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+ /* If legacy MMIO hole enabled */
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+ if (lgcy_mmio_hole_en) {
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+ if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
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+ goto out_err;
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+
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+ dram_hole_base = tmp & GENMASK(31, 24);
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+ if (ret_addr >= dram_hole_base)
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+ ret_addr += (BIT_ULL(32) - dram_hole_base);
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+ }
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+
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+ if (hash_enabled) {
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+ /* Save some parentheses and grab ls-bit at the end. */
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+ hashed_bit = (ret_addr >> 12) ^
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+ (ret_addr >> 18) ^
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+ (ret_addr >> 21) ^
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+ (ret_addr >> 30) ^
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+ cs_id;
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+
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+ hashed_bit &= BIT(0);
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+
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+ if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
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+ ret_addr ^= BIT(intlv_addr_bit);
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+ }
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+
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+ /* Is calculated system address is above DRAM limit address? */
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+ if (ret_addr > dram_limit_addr)
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+ goto out_err;
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+
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+ *sys_addr = ret_addr;
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+ return 0;
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+
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+out_err:
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
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+
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static void
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__log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
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{
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@@ -645,6 +865,7 @@ static void amd_threshold_interrupt(void)
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{
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u32 low = 0, high = 0, address = 0;
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unsigned int bank, block, cpu = smp_processor_id();
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+ struct thresh_restart tr;
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/* assume first bank caused it */
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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@@ -681,6 +902,11 @@ static void amd_threshold_interrupt(void)
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log:
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__log_error(bank, false, true, ((u64)high << 32) | low);
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+
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+ /* Reset threshold block after logging error. */
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+ memset(&tr, 0, sizeof(tr));
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+ tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block];
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+ threshold_restart_bank(&tr);
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}
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/*
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@@ -826,10 +1052,10 @@ static const char *get_name(unsigned int bank, struct threshold_block *b)
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return th_names[bank];
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}
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- if (!smca_banks[bank].type)
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+ if (!smca_banks[bank].hwid)
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return NULL;
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- bank_type = smca_banks[bank].type->bank_type;
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+ bank_type = smca_banks[bank].hwid->bank_type;
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if (b && bank_type == SMCA_UMC) {
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if (b->block < ARRAY_SIZE(smca_umc_block_names))
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@@ -838,8 +1064,8 @@ static const char *get_name(unsigned int bank, struct threshold_block *b)
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}
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snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
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- "%s_%x", smca_bank_names[bank_type].name,
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- smca_banks[bank].type_instance);
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+ "%s_%x", smca_get_name(bank_type),
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+ smca_banks[bank].id);
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return buf_mcatype;
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}
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Linus Torvalds