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@@ -0,0 +1,54 @@
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+NXP LPC18xx/43xx DMA MUX (DMA request router)
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+
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+Required properties:
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+- compatible: "nxp,lpc1850-dmamux"
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+- reg: Memory map for accessing module
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+- #dma-cells: Should be set to <3>.
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+ * 1st cell contain the master dma request signal
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+ * 2nd cell contain the mux value (0-3) for the peripheral
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+ * 3rd cell contain either 1 or 2 depending on the AHB
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+ master used.
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+- dma-requests: Number of DMA requests for the mux
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+- dma-masters: phandle pointing to the DMA controller
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+
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+The DMA controller node need to have the following poroperties:
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+- dma-requests: Number of DMA requests the controller can handle
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+
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+Example:
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+
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+dmac: dma@40002000 {
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+ compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
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+ arm,primecell-periphid = <0x00041080>;
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+ reg = <0x40002000 0x1000>;
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+ interrupts = <2>;
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+ clocks = <&ccu1 CLK_CPU_DMA>;
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+ clock-names = "apb_pclk";
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+ #dma-cells = <2>;
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+ dma-channels = <8>;
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+ dma-requests = <16>;
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+ lli-bus-interface-ahb1;
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+ lli-bus-interface-ahb2;
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+ mem-bus-interface-ahb1;
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+ mem-bus-interface-ahb2;
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+ memcpy-burst-size = <256>;
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+ memcpy-bus-width = <32>;
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+};
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+
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+dmamux: dma-mux {
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+ compatible = "nxp,lpc1850-dmamux";
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+ #dma-cells = <3>;
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+ dma-requests = <64>;
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+ dma-masters = <&dmac>;
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+};
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+
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+uart0: serial@40081000 {
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+ compatible = "nxp,lpc1850-uart", "ns16550a";
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+ reg = <0x40081000 0x1000>;
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+ reg-shift = <2>;
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+ interrupts = <24>;
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+ clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
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+ clock-names = "uartclk", "reg";
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+ dmas = <&dmamux 1 1 2
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+ &dmamux 2 1 2>;
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+ dma-names = "tx", "rx";
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+};
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