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@@ -22,18 +22,12 @@
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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-#include "soc.h"
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#include "generic.h"
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#include "pm.h"
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-struct at91_init_soc __initdata at91_boot_soc;
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-
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struct at91_socinfo at91_soc_initdata;
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EXPORT_SYMBOL(at91_soc_initdata);
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-void __iomem *at91_ramc_base[2];
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-EXPORT_SYMBOL_GPL(at91_ramc_base);
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-
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static struct map_desc at91_io_desc __initdata __maybe_unused = {
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.virtual = (unsigned long)AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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@@ -60,61 +54,51 @@ static void __init soc_detect(u32 dbgu_base)
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at91_soc_initdata.type = AT91_SOC_RM9200;
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if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
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at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
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- at91_boot_soc = at91rm9200_soc;
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break;
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case ARCH_ID_AT91SAM9260:
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at91_soc_initdata.type = AT91_SOC_SAM9260;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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- at91_boot_soc = at91sam9260_soc;
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break;
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case ARCH_ID_AT91SAM9261:
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at91_soc_initdata.type = AT91_SOC_SAM9261;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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- at91_boot_soc = at91sam9261_soc;
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break;
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case ARCH_ID_AT91SAM9263:
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at91_soc_initdata.type = AT91_SOC_SAM9263;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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- at91_boot_soc = at91sam9263_soc;
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break;
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case ARCH_ID_AT91SAM9G20:
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at91_soc_initdata.type = AT91_SOC_SAM9G20;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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- at91_boot_soc = at91sam9260_soc;
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break;
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case ARCH_ID_AT91SAM9G45:
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at91_soc_initdata.type = AT91_SOC_SAM9G45;
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if (cidr == ARCH_ID_AT91SAM9G45ES)
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at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
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- at91_boot_soc = at91sam9g45_soc;
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break;
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case ARCH_ID_AT91SAM9RL64:
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at91_soc_initdata.type = AT91_SOC_SAM9RL;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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- at91_boot_soc = at91sam9rl_soc;
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break;
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case ARCH_ID_AT91SAM9X5:
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at91_soc_initdata.type = AT91_SOC_SAM9X5;
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- at91_boot_soc = at91sam9x5_soc;
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break;
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case ARCH_ID_AT91SAM9N12:
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at91_soc_initdata.type = AT91_SOC_SAM9N12;
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- at91_boot_soc = at91sam9n12_soc;
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break;
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case ARCH_ID_SAMA5:
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at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
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if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
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at91_soc_initdata.type = AT91_SOC_SAMA5D3;
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- at91_boot_soc = sama5d3_soc;
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}
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break;
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}
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@@ -123,13 +107,11 @@ static void __init soc_detect(u32 dbgu_base)
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if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
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at91_soc_initdata.type = AT91_SOC_SAM9G10;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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- at91_boot_soc = at91sam9261_soc;
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}
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/* at91sam9xe */
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else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
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at91_soc_initdata.type = AT91_SOC_SAM9260;
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at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
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- at91_boot_soc = at91sam9260_soc;
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}
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if (!at91_soc_is_detected())
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@@ -209,10 +191,8 @@ static void __init alt_soc_detect(u32 dbgu_base)
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at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
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if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
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at91_soc_initdata.type = AT91_SOC_SAMA5D3;
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- at91_boot_soc = sama5d3_soc;
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} else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
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at91_soc_initdata.type = AT91_SOC_SAMA5D4;
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- at91_boot_soc = sama5d4_soc;
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}
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break;
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}
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@@ -318,12 +298,6 @@ void __init at91_map_io(void)
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if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
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pr_info("Detected soc subtype: %s\n",
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at91_get_soc_subtype(&at91_soc_initdata));
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-
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- if (!at91_soc_is_enabled())
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- panic(pr_fmt("Soc not enabled"));
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-
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- if (at91_boot_soc.map_io)
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- at91_boot_soc.map_io();
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}
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void __init at91_alt_map_io(void)
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@@ -343,12 +317,6 @@ void __init at91_alt_map_io(void)
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if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
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pr_info("AT91: Detected soc subtype: %s\n",
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at91_get_soc_subtype(&at91_soc_initdata));
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-
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- if (!at91_soc_is_enabled())
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- panic("AT91: Soc not enabled");
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-
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- if (at91_boot_soc.map_io)
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- at91_boot_soc.map_io();
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}
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void __iomem *at91_matrix_base;
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@@ -360,48 +328,3 @@ void __init at91_ioremap_matrix(u32 base_addr)
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if (!at91_matrix_base)
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panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
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}
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-
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-static struct of_device_id ramc_ids[] = {
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- { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
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- { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
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- { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
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- { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
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- { /*sentinel*/ }
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-};
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-
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-static void at91_dt_ramc(void)
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-{
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- struct device_node *np;
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- const struct of_device_id *of_id;
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- int idx = 0;
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- const void *standby = NULL;
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-
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- for_each_matching_node_and_match(np, ramc_ids, &of_id) {
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- at91_ramc_base[idx] = of_iomap(np, 0);
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- if (!at91_ramc_base[idx])
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- panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
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-
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- if (!standby)
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- standby = of_id->data;
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-
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- idx++;
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- }
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-
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- if (!idx)
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- panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
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-
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- if (!standby) {
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- pr_warn("ramc no standby function available\n");
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- return;
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- }
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-
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- at91_pm_set_standby(standby);
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-}
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-
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-void __init at91_dt_initialize(void)
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-{
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- at91_dt_ramc();
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-
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- if (at91_boot_soc.init)
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- at91_boot_soc.init();
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-}
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