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@@ -865,6 +865,64 @@ static void svm_disable_lbrv(struct vcpu_svm *svm)
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set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
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}
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+#define MTRR_TYPE_UC_MINUS 7
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+#define MTRR2PROTVAL_INVALID 0xff
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+
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+static u8 mtrr2protval[8];
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+
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+static u8 fallback_mtrr_type(int mtrr)
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+{
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+ /*
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+ * WT and WP aren't always available in the host PAT. Treat
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+ * them as UC and UC- respectively. Everything else should be
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+ * there.
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+ */
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+ switch (mtrr)
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+ {
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+ case MTRR_TYPE_WRTHROUGH:
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+ return MTRR_TYPE_UNCACHABLE;
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+ case MTRR_TYPE_WRPROT:
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+ return MTRR_TYPE_UC_MINUS;
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+ default:
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+ BUG();
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+ }
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+}
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+
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+static void build_mtrr2protval(void)
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+{
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+ int i;
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+ u64 pat;
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+
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+ for (i = 0; i < 8; i++)
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+ mtrr2protval[i] = MTRR2PROTVAL_INVALID;
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+
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+ /* Ignore the invalid MTRR types. */
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+ mtrr2protval[2] = 0;
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+ mtrr2protval[3] = 0;
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+
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+ /*
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+ * Use host PAT value to figure out the mapping from guest MTRR
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+ * values to nested page table PAT/PCD/PWT values. We do not
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+ * want to change the host PAT value every time we enter the
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+ * guest.
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+ */
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+ rdmsrl(MSR_IA32_CR_PAT, pat);
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+ for (i = 0; i < 8; i++) {
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+ u8 mtrr = pat >> (8 * i);
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+
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+ if (mtrr2protval[mtrr] == MTRR2PROTVAL_INVALID)
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+ mtrr2protval[mtrr] = __cm_idx2pte(i);
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+ }
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+
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+ for (i = 0; i < 8; i++) {
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+ if (mtrr2protval[i] == MTRR2PROTVAL_INVALID) {
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+ u8 fallback = fallback_mtrr_type(i);
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+ mtrr2protval[i] = mtrr2protval[fallback];
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+ BUG_ON(mtrr2protval[i] == MTRR2PROTVAL_INVALID);
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+ }
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+ }
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+}
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+
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static __init int svm_hardware_setup(void)
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{
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int cpu;
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@@ -931,6 +989,7 @@ static __init int svm_hardware_setup(void)
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} else
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kvm_disable_tdp();
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+ build_mtrr2protval();
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return 0;
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err:
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@@ -1085,6 +1144,39 @@ static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
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return target_tsc - tsc;
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}
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+static void svm_set_guest_pat(struct vcpu_svm *svm, u64 *g_pat)
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+{
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+ struct kvm_vcpu *vcpu = &svm->vcpu;
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+
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+ /* Unlike Intel, AMD takes the guest's CR0.CD into account.
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+ *
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+ * AMD does not have IPAT. To emulate it for the case of guests
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+ * with no assigned devices, just set everything to WB. If guests
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+ * have assigned devices, however, we cannot force WB for RAM
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+ * pages only, so use the guest PAT directly.
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+ */
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+ if (!kvm_arch_has_assigned_device(vcpu->kvm))
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+ *g_pat = 0x0606060606060606;
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+ else
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+ *g_pat = vcpu->arch.pat;
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+}
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+
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+static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
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+{
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+ u8 mtrr;
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+
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+ /*
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+ * 1. MMIO: trust guest MTRR, so same as item 3.
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+ * 2. No passthrough: always map as WB, and force guest PAT to WB as well
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+ * 3. Passthrough: can't guarantee the result, try to trust guest.
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+ */
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+ if (!is_mmio && !kvm_arch_has_assigned_device(vcpu->kvm))
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+ return 0;
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+
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+ mtrr = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
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+ return mtrr2protval[mtrr];
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+}
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+
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static void init_vmcb(struct vcpu_svm *svm, bool init_event)
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{
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struct vmcb_control_area *control = &svm->vmcb->control;
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@@ -1180,6 +1272,7 @@ static void init_vmcb(struct vcpu_svm *svm, bool init_event)
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clr_cr_intercept(svm, INTERCEPT_CR3_READ);
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clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
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save->g_pat = svm->vcpu.arch.pat;
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+ svm_set_guest_pat(svm, &save->g_pat);
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save->cr3 = 0;
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save->cr4 = 0;
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}
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@@ -3254,6 +3347,16 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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case MSR_VM_IGNNE:
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vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
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break;
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+ case MSR_IA32_CR_PAT:
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+ if (npt_enabled) {
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+ if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
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+ return 1;
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+ vcpu->arch.pat = data;
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+ svm_set_guest_pat(svm, &svm->vmcb->save.g_pat);
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+ mark_dirty(svm->vmcb, VMCB_NPT);
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+ break;
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+ }
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+ /* fall through */
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default:
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return kvm_set_msr_common(vcpu, msr);
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}
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@@ -4088,11 +4191,6 @@ static bool svm_has_high_real_mode_segbase(void)
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return true;
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}
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-static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
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-{
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- return 0;
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-}
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-
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static void svm_cpuid_update(struct kvm_vcpu *vcpu)
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{
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}
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