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@@ -524,6 +524,18 @@ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, ib->length_dw);
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}
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+static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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+{
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+ int i;
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+
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+ WARN_ON(ring->wptr % 2 || count % 2);
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+
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+ for (i = 0; i < count / 2; i++) {
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+ amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
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+ amdgpu_ring_write(ring, 0);
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+ }
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+}
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+
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/**
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* uvd_v4_2_mc_resume - memory controller programming
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*
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@@ -733,7 +745,6 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
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static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
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.type = AMDGPU_RING_TYPE_UVD,
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.align_mask = 0xf,
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- .nop = PACKET0(mmUVD_NO_OP, 0),
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.support_64bit_ptrs = false,
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.get_rptr = uvd_v4_2_ring_get_rptr,
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.get_wptr = uvd_v4_2_ring_get_wptr,
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@@ -746,7 +757,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
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.emit_fence = uvd_v4_2_ring_emit_fence,
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.test_ring = uvd_v4_2_ring_test_ring,
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.test_ib = amdgpu_uvd_ring_test_ib,
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- .insert_nop = amdgpu_ring_insert_nop,
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+ .insert_nop = uvd_v4_2_ring_insert_nop,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_uvd_ring_begin_use,
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.end_use = amdgpu_uvd_ring_end_use,
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